Liphen
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ca1a6abe7b
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修复mem被阻塞时读数据错误问题
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2024-05-11 14:49:38 +08:00 |
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Liphen
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5bd7124535
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feat(debug): 增加sram差分测试接口
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2024-05-11 11:40:26 +08:00 |
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Liphen
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4a9e3dc05f
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修改debug信号的wen为commit
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2024-05-09 19:16:02 +08:00 |
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Liphen
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be93752841
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修复jalr指令跳转目标问题
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2024-05-08 20:44:30 +08:00 |
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Liphen
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4f32948d0b
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修复访存级的冲刷问题
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2024-05-08 20:01:21 +08:00 |
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Liphen
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ed586e41b6
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fix: Fix FetchUnit PC initialization issue
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2024-05-08 16:56:28 +08:00 |
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Liphen
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9862402688
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fix: Fix FetchUnit PC initialization issue
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2024-05-08 13:04:57 +08:00 |
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Liphen
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333ced6e19
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fix(if): 修复第一个pc初始值问题
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2024-05-06 16:05:40 +08:00 |
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Liphen
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64336aaf1c
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refactor: 将ex信息在执行级后省略
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2024-03-22 23:29:02 +08:00 |
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Liphen
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be91a70924
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修改TestMain
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2024-03-22 23:18:11 +08:00 |
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Liphen
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e955c3d580
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更改CpuConfig
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2024-03-22 23:16:48 +08:00 |
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Liphen
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81b3915c46
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feat: 成功生成sram的verilog
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2024-03-22 22:57:04 +08:00 |
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Liphen
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0a20a7cda9
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feat: 升级chisel版本至5.0
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2024-03-22 22:56:41 +08:00 |
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Liphen
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6508b72858
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修改包名，修改各单元逻辑
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2024-03-22 22:45:48 +08:00 |
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Liphen
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703cd0b41c
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修改wb
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2024-03-22 21:14:19 +08:00 |
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Liphen
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8520961a64
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修改lsu
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2024-03-22 21:11:58 +08:00 |
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Liphen
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d16b70ea8d
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修改CpuConfig
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2024-03-22 15:07:18 +08:00 |
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Liphen
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f43763b32c
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修改bru，去除分支预测
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2024-03-22 15:00:13 +08:00 |
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Liphen
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e6decd7c82
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修改mdu
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2024-03-22 14:26:21 +08:00 |
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Liphen
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1ab2644cba
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修改if级逻辑
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2024-03-22 14:23:37 +08:00 |
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Liphen
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a69e4e907d
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删除不必要的文件
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2024-03-22 14:23:12 +08:00 |
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Liphen
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7e13a02cb4
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修改id级逻辑
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2024-03-22 14:18:56 +08:00 |
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Liphen
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2c7af2ce4b
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增加sram的顶层接口
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2024-03-22 11:13:19 +08:00 |
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Liphen
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b782293dac
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refactor: 修改异常变量名称
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2024-03-11 20:03:33 +08:00 |
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Liphen
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32005bb3e2
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删去部分无用定义
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2024-03-11 19:46:55 +08:00 |
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Liphen
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aaf97820d4
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fix(csr): 修复mem级valid无效时仍使用ex信息
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2024-03-11 19:27:23 +08:00 |
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Liphen
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68dd1be7ac
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refactor(csr): 修改特权指令的解码赋值
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2024-03-11 19:26:26 +08:00 |
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Liphen
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f7fb3c4677
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fix(icache): 当地址未对齐时不应访存
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2024-03-09 16:12:56 +08:00 |
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Liphen
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5e7a2eb162
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fix(csr): 在某些条件下重置mprv
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2024-03-08 17:28:01 +08:00 |
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Liphen
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51189b0d38
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fix(csr): 修改mip掩码
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2024-03-01 12:55:44 +08:00 |
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Liphen
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fdc8c2b11e
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refactor(core): 修改clear信号，使逻辑更清晰
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2024-02-25 17:09:12 +08:00 |
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Liphen
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3b06ee4f55
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fix(fu): 修复sc地址前递bug
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2024-02-25 16:53:09 +08:00 |
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Liphen
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59db6ed7cd
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fix(ctrl): 删除无用信号
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2024-02-25 16:06:27 +08:00 |
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Liphen
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6ccd13ee47
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refactor: 重构实验目录结构
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2024-02-03 11:34:41 +08:00 |
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Liphen
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ea7ce1cab9
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增加lab11和lab12
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2024-02-01 13:39:14 +08:00 |
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Liphen
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678710a80d
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instinfo改为info
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2024-01-27 17:20:27 +08:00 |
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Liphen
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22b417a99e
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修改mdu的start为en
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2024-01-27 16:16:03 +08:00 |
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Liphen
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9c3e70a3f4
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重构instfifo
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2024-01-23 14:38:47 +08:00 |
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Liphen
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8b4f9c71dd
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refactor: 大致完成cpu的重构
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2024-01-23 13:08:06 +08:00 |
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Liphen
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1effd2929a
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重构lsExecute
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2024-01-22 16:50:45 +08:00 |
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Liphen
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2e774df884
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重构lsu
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2024-01-22 16:43:02 +08:00 |
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Liphen
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33e20fa99c
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重构mem unit
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2024-01-22 16:20:06 +08:00 |
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Liphen
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7ee50481a9
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重构issue
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2024-01-22 15:56:12 +08:00 |
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Liphen
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413a7e22d2
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重构exe unit
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2024-01-22 15:40:38 +08:00 |
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Liphen
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b13ff2377c
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简单重构wb stage级接口
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2024-01-22 15:11:24 +08:00 |
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Liphen
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2c63e880ea
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重构mem stage级接口
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2024-01-22 14:17:20 +08:00 |
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Liphen
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4448b9639b
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重构exe stage级接口
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2024-01-22 14:09:22 +08:00 |
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Liphen
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2bff20053d
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fix(csr): stval只在deleg的情况下更新
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2024-01-21 13:57:45 +08:00 |
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Liphen
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2a09884e0f
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fix(fu): 修改地址前递逻辑
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2024-01-21 13:51:46 +08:00 |
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Liphen
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c6d8f9ed8f
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fix(dcache): 解决写回时数据备份问题
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2024-01-21 12:37:50 +08:00 |