修改id级逻辑
This commit is contained in:
Liphen
parent
2c7af2ce4b
commit
7e13a02cb4
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@ -24,43 +24,35 @@ class RegWrite extends Bundle {
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class ARegFile(implicit val cpuConfig: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val read = Flipped(Vec(cpuConfig.decoderNum, new Src12Read()))
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val write = Flipped(Vec(cpuConfig.commitNum, new RegWrite()))
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val read = Flipped(new Src12Read())
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val write = Flipped(new RegWrite())
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})
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// 定义32个32位寄存器
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val regs = RegInit(VecInit(Seq.fill(AREG_NUM)(0.U(XLEN.W))))
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// 写寄存器堆
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for (i <- 0 until (cpuConfig.commitNum)) {
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when(io.write(i).wen && io.write(i).waddr =/= 0.U) {
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regs(io.write(i).waddr) := io.write(i).wdata
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}
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when(io.write.wen && io.write.waddr =/= 0.U) {
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regs(io.write.waddr) := io.write.wdata
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}
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// 读寄存器堆
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for (i <- 0 until (cpuConfig.decoderNum)) {
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// src1
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when(io.read(i).src1.raddr === 0.U) {
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io.read(i).src1.rdata := 0.U
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}.otherwise {
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io.read(i).src1.rdata := regs(io.read(i).src1.raddr)
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for (j <- 0 until (cpuConfig.commitNum)) {
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when(io.write(j).wen && io.read(i).src1.raddr === io.write(j).waddr) {
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io.read(i).src1.rdata := io.write(j).wdata
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}
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}
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// src1
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when(io.read.src1.raddr === 0.U) {
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io.read.src1.rdata := 0.U
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}.otherwise {
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io.read.src1.rdata := regs(io.read.src1.raddr)
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when(io.write.wen && io.read.src1.raddr === io.write.waddr) {
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io.read.src1.rdata := io.write.wdata
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}
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// src2
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when(io.read(i).src2.raddr === 0.U) {
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io.read(i).src2.rdata := 0.U
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}.otherwise {
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io.read(i).src2.rdata := regs(io.read(i).src2.raddr)
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for (j <- 0 until (cpuConfig.commitNum)) {
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when(io.write(j).wen && io.read(i).src2.raddr === io.write(j).waddr) {
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io.read(i).src2.rdata := io.write(j).wdata
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}
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}
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}
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// src2
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when(io.read.src2.raddr === 0.U) {
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io.read.src2.rdata := 0.U
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}.otherwise {
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io.read.src2.rdata := regs(io.read.src2.raddr)
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when(io.write.wen && io.read.src2.raddr === io.write.waddr) {
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io.read.src2.rdata := io.write.wdata
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}
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}
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}
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@ -0,0 +1,38 @@
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package cpu.pipeline.decode
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import chisel3._
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import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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class IfIdData extends Bundle {
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val inst = UInt(XLEN.W)
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val valid = Bool()
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val pc = UInt(XLEN.W)
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val addr_misaligned = Bool()
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}
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class FetchUnitDecodeUnit extends IfIdData {
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val data = Output(new IfIdData())
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}
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class DecodeStage(implicit val cpuConfig: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val ctrl = Input(new Bundle {
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val allow_to_go = Bool()
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val clear = Bool()
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})
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val fetchUnit = Flipped(new FetchUnitDecodeUnit())
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val decodeUnit = new FetchUnitDecodeUnit()
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})
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val data = RegInit(0.U.asTypeOf(new IfIdData()))
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when(io.ctrl.clear) {
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data := 0.U.asTypeOf(new IfIdData())
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}.elsewhen(io.ctrl.allow_to_go) {
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data := io.fetchUnit
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}
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io.decodeUnit.data := data
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}
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@ -5,148 +5,60 @@ import chisel3.util._
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import chisel3.util.experimental.BoringUtils
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.{BranchPredictorConfig, CpuConfig}
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import cpu.pipeline.execute.DecodeUnitExecuteUnit
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import cpu.pipeline.fetch.IfIdData
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import cpu.pipeline.execute
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class DecodeUnitInstFifo(implicit val cpuConfig: CpuConfig) extends Bundle {
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val allow_to_go = Output(Vec(cpuConfig.decoderNum, Bool()))
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val inst = Input(Vec(cpuConfig.decoderNum, new IfIdData()))
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val info = Input(new Bundle {
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val empty = Bool()
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val almost_empty = Bool()
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})
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}
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class DataForwardToDecodeUnit extends Bundle {
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val exe = new RegWrite()
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val is_load = Bool()
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val mem = new RegWrite()
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}
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class DecoderBranchPredictorUnit extends Bundle {
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val bpuConfig = new BranchPredictorConfig()
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val pc = Output(UInt(XLEN.W))
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val info = Output(new Info())
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val pht_index = Output(UInt(bpuConfig.phtDepth.W))
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val branch_inst = Input(Bool())
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val branch = Input(Bool())
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val target = Input(UInt(XLEN.W))
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val update_pht_index = Input(UInt(bpuConfig.phtDepth.W))
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}
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class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExceptionNO with HasCSRConst {
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class DecodeUnit extends Module with HasExceptionNO with HasCSRConst {
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val io = IO(new Bundle {
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// 输入
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val instFifo = new DecodeUnitInstFifo()
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val regfile = Vec(cpuConfig.decoderNum, new Src12Read())
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val forward = Input(Vec(cpuConfig.commitNum, new DataForwardToDecodeUnit()))
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val csr = Input(new execute.CsrDecodeUnit())
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val decodeStage = Flipped(new FetchUnitDecodeUnit())
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val regfile = new Src12Read()
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val forward = Input(new DataForwardToDecodeUnit())
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// 输出
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val fetchUnit = new Bundle {
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val branch = Output(Bool())
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val target = Output(UInt(XLEN.W))
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}
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val bpu = new DecoderBranchPredictorUnit()
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val executeStage = Output(new DecodeUnitExecuteUnit())
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val ctrl = new DecodeUnitCtrl()
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})
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val decoder = Seq.fill(cpuConfig.decoderNum)(Module(new Decoder()))
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val jumpCtrl = Module(new JumpCtrl()).io
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val decoder = Module(new Decoder())
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val forwardCtrl = Module(new ForwardCtrl()).io
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val issue = Module(new Issue()).io
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val pc = io.instFifo.inst.map(_.pc)
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val inst = io.instFifo.inst.map(_.inst)
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val info = Wire(Vec(cpuConfig.decoderNum, new Info()))
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val mode = io.csr.mode
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val pc = io.decodeStage.data.pc
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val info = Wire(new Info())
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info := decoder.map(_.io.out.info)
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info(0).valid := !io.instFifo.info.empty
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info(1).valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty
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issue.allow_to_go := io.ctrl.allow_to_go
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issue.instFifo := io.instFifo.info
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io.instFifo.allow_to_go(1) := issue.inst1.allow_to_go
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for (i <- 0 until (cpuConfig.decoderNum)) {
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decoder(i).io.in.inst := inst(i)
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issue.decodeInst(i) := info(i)
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issue.execute(i).is_load := io.forward(i).is_load
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issue.execute(i).reg_waddr := io.forward(i).exe.waddr
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io.regfile(i).src1.raddr := info(i).src1_raddr
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io.regfile(i).src2.raddr := info(i).src2_raddr
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}
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info := decoder.io.out.info
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info.valid := io.decodeStage.data.valid
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forwardCtrl.in.forward := io.forward
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forwardCtrl.in.regfile := io.regfile
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jumpCtrl.in.info := info(0)
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jumpCtrl.in.forward := io.forward
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jumpCtrl.in.pc := pc(0)
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jumpCtrl.in.src_info := io.executeStage.inst(0).src_info
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val inst0_branch = jumpCtrl.out.jump || io.bpu.branch
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io.ctrl.src_info.src1.ren := info.src1_ren
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io.ctrl.src_info.src1.raddr := info.src1_raddr
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io.ctrl.src_info.src2.ren := info.src2_ren
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io.ctrl.src_info.src2.raddr := info.src2_raddr
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io.ctrl.branch := io.fetchUnit.branch
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io.fetchUnit.branch := inst0_branch && io.ctrl.allow_to_go
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io.fetchUnit.target := Mux(io.bpu.branch, io.bpu.target, jumpCtrl.out.jump_target)
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io.instFifo.allow_to_go(0) := io.ctrl.allow_to_go
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io.bpu.pc := pc(0)
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io.bpu.info := info(0)
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io.bpu.pht_index := io.instFifo.inst(0).pht_index
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io.ctrl.inst0.src1.ren := info(0).src1_ren
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io.ctrl.inst0.src1.raddr := info(0).src1_raddr
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io.ctrl.inst0.src2.ren := info(0).src2_ren
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io.ctrl.inst0.src2.raddr := info(0).src2_raddr
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io.ctrl.branch := io.fetchUnit.branch
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io.executeStage.jump_branch_info.jump_regiser := jumpCtrl.out.jump_register
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io.executeStage.jump_branch_info.branch_inst := io.bpu.branch_inst
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io.executeStage.jump_branch_info.pred_branch := io.bpu.branch
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io.executeStage.jump_branch_info.branch_target := io.bpu.target
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io.executeStage.jump_branch_info.update_pht_index := io.bpu.update_pht_index
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for (i <- 0 until (cpuConfig.commitNum)) {
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io.executeStage.inst(i).pc := pc(i)
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io.executeStage.inst(i).info := info(i)
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io.executeStage.inst(i).src_info.src1_data := MuxCase(
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SignedExtend(pc(i), XLEN),
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Seq(
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info(i).src1_ren -> forwardCtrl.out.inst(i).src1.rdata,
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(info(i).inst(6, 0) === "b0110111".U) -> 0.U
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)
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io.executeStage.data.pc := pc
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io.executeStage.data.info := info
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io.executeStage.data.src_info.src1_data := MuxCase(
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SignedExtend(pc, XLEN),
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Seq(
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info.src1_ren -> forwardCtrl.out.data.src1.rdata,
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(info.inst(6, 0) === "b0110111".U) -> 0.U
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)
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io.executeStage.inst(i).src_info.src2_data := Mux(
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info(i).src2_ren,
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forwardCtrl.out.inst(i).src2.rdata,
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info(i).imm
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)
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(0 until (INT_WID)).foreach(j => io.executeStage.inst(i).ex.interrupt(j) := io.csr.interrupt(j))
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io.executeStage.inst(i).ex.exception.map(_ := false.B)
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io.executeStage.inst(i).ex.exception(illegalInst) := !info(i).inst_legal
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io.executeStage.inst(i).ex.exception(instAccessFault) := io.instFifo.inst(i).access_fault
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io.executeStage.inst(i).ex.exception(instPageFault) := io.instFifo.inst(i).page_fault
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io.executeStage.inst(i).ex.exception(instAddrMisaligned) := io.instFifo.inst(i).addr_misaligned ||
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io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch
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io.executeStage.inst(i).ex.exception(breakPoint) :=
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info(i).op === CSROpType.ebreak && info(i).fusel === FuType.csr
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io.executeStage.inst(i).ex.exception(ecallM) :=
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info(i).op === CSROpType.ecall && mode === ModeM && info(i).fusel === FuType.csr
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io.executeStage.inst(i).ex.exception(ecallS) :=
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info(i).op === CSROpType.ecall && mode === ModeS && info(i).fusel === FuType.csr
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io.executeStage.inst(i).ex.exception(ecallU) :=
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info(i).op === CSROpType.ecall && mode === ModeU && info(i).fusel === FuType.csr
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io.executeStage.inst(i).ex.tval.map(_ := DontCare)
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io.executeStage.inst(i).ex.tval(instPageFault) := pc(i)
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io.executeStage.inst(i).ex.tval(instAccessFault) := pc(i)
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io.executeStage.inst(i).ex.tval(illegalInst) := info(i).inst
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io.executeStage.inst(i).ex.tval(instAddrMisaligned) := Mux(
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io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch,
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io.fetchUnit.target,
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pc(i)
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)
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}
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)
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io.executeStage.data.src_info.src2_data := Mux(
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info.src2_ren,
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forwardCtrl.out.data.src2.rdata,
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info.imm
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)
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}
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@ -7,68 +7,56 @@ import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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class ForwardCtrl(implicit val cpuConfig: CpuConfig) extends Module {
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class ForwardCtrl extends Module {
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val io = IO(new Bundle {
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val in = Input(new Bundle {
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val forward = Vec(cpuConfig.commitNum, new DataForwardToDecodeUnit())
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val regfile = Vec(cpuConfig.decoderNum, new Src12Read())
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val forward = new DataForwardToDecodeUnit()
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val regfile = new Src12Read()
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})
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val out = Output(new Bundle {
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val inst = Vec(cpuConfig.decoderNum, new Src12Read())
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val data = new Src12Read()
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})
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})
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// wb优先度最低
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for (i <- 0 until (cpuConfig.decoderNum)) {
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io.out.inst(i).src1.raddr := DontCare
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io.out.inst(i).src2.raddr := DontCare
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io.out.inst(i).src1.rdata := io.in.regfile(i).src1.rdata
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io.out.inst(i).src2.rdata := io.in.regfile(i).src2.rdata
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}
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io.out.data.src1.raddr := DontCare
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io.out.data.src2.raddr := DontCare
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io.out.data.src1.rdata := io.in.regfile.src1.rdata
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io.out.data.src2.rdata := io.in.regfile.src2.rdata
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// mem优先度中
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for (i <- 0 until (cpuConfig.decoderNum)) {
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for (j <- 0 until (cpuConfig.commitNum)) {
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when(
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io.in.forward(j).mem.wen &&
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io.in.forward(j).mem.waddr === io.in.regfile(i).src1.raddr
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) {
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io.out.inst(i).src1.rdata := io.in.forward(j).mem.wdata
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}
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when(
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io.in.forward(j).mem.wen &&
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io.in.forward(j).mem.waddr === io.in.regfile(i).src2.raddr
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) {
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io.out.inst(i).src2.rdata := io.in.forward(j).mem.wdata
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}
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}
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when(
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io.in.forward.mem.wen &&
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io.in.forward.mem.waddr === io.in.regfile.src1.raddr
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) {
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io.out.data.src1.rdata := io.in.forward.mem.wdata
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}
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when(
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io.in.forward.mem.wen &&
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io.in.forward.mem.waddr === io.in.regfile.src2.raddr
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) {
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io.out.data.src2.rdata := io.in.forward.mem.wdata
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}
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// exe优先度高
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for (i <- 0 until (cpuConfig.decoderNum)) {
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for (j <- 0 until (cpuConfig.commitNum)) {
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when(
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io.in.forward(j).exe.wen && !io.in.forward(j).is_load &&
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io.in.forward(j).exe.waddr === io.in.regfile(i).src1.raddr
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) {
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io.out.inst(i).src1.rdata := io.in.forward(j).exe.wdata
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}
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when(
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io.in.forward(j).exe.wen && !io.in.forward(j).is_load &&
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io.in.forward(j).exe.waddr === io.in.regfile(i).src2.raddr
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) {
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io.out.inst(i).src2.rdata := io.in.forward(j).exe.wdata
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}
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}
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when(
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io.in.forward.exe.wen && !io.in.forward.is_load &&
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io.in.forward.exe.waddr === io.in.regfile.src1.raddr
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) {
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io.out.data.src1.rdata := io.in.forward.exe.wdata
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}
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when(
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io.in.forward.exe.wen && !io.in.forward.is_load &&
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io.in.forward.exe.waddr === io.in.regfile.src2.raddr
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) {
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io.out.data.src2.rdata := io.in.forward.exe.wdata
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}
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// 读零寄存器时，数据为0
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(0 until (cpuConfig.decoderNum)).foreach(i => {
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when(io.in.regfile(i).src1.raddr === 0.U) {
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io.out.inst(i).src1.rdata := 0.U
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}
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when(io.in.regfile(i).src2.raddr === 0.U) {
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io.out.inst(i).src2.rdata := 0.U
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}
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})
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when(io.in.regfile.src1.raddr === 0.U) {
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io.out.data.src1.rdata := 0.U
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}
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when(io.in.regfile.src2.raddr === 0.U) {
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io.out.data.src2.rdata := 0.U
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}
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}
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