59 lines
1.4 KiB
Scala
59 lines
1.4 KiB
Scala
package cpu.pipeline.decode
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import chisel3._
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import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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class SrcRead extends Bundle {
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val raddr = Output(UInt(REG_ADDR_WID.W))
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val rdata = Input(UInt(XLEN.W))
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}
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class Src12Read extends Bundle {
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val src1 = new SrcRead()
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val src2 = new SrcRead()
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}
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class RegWrite extends Bundle {
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val wen = Output(Bool())
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val waddr = Output(UInt(REG_ADDR_WID.W))
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val wdata = Output(UInt(XLEN.W))
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}
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class ARegFile(implicit val cpuConfig: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val read = Flipped(new Src12Read())
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val write = Flipped(new RegWrite())
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})
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// 定义32个32位寄存器
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val regs = RegInit(VecInit(Seq.fill(AREG_NUM)(0.U(XLEN.W))))
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// 写寄存器堆
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when(io.write.wen && io.write.waddr =/= 0.U) {
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regs(io.write.waddr) := io.write.wdata
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}
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// 读寄存器堆
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// src1
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when(io.read.src1.raddr === 0.U) {
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io.read.src1.rdata := 0.U
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}.otherwise {
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io.read.src1.rdata := regs(io.read.src1.raddr)
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when(io.write.wen && io.read.src1.raddr === io.write.waddr) {
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io.read.src1.rdata := io.write.wdata
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}
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}
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// src2
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when(io.read.src2.raddr === 0.U) {
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io.read.src2.rdata := 0.U
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}.otherwise {
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io.read.src2.rdata := regs(io.read.src2.raddr)
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when(io.write.wen && io.read.src2.raddr === io.write.waddr) {
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io.read.src2.rdata := io.write.wdata
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}
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}
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}
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