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fix(fu): 修复sc地址前递bug

This commit is contained in:
Liphen 2024-02-25 16:53:09 +08:00
parent 59db6ed7cd
commit 3b06ee4f55
1 changed files with 1 additions and 1 deletions
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2
chisel/playground/src/pipeline/execute/Fu.scala
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@ -80,7 +80,7 @@ class Fu(implicit val cpuConfig: CpuConfig) extends Module {
val mem_addr = Seq.tabulate(cpuConfig.commitNum)(i =>
Mux(
LSUOpType.isAMO(io.inst(i).info.op) || LSUOpType.isLR(io.inst(i).info.op),
LSUOpType.isAtom(io.inst(i).info.op),
io.inst(i).src_info.src1_data,
io.inst(i).src_info.src1_data + io.inst(i).info.imm
)