From 3b06ee4f55052929d8584f574ec0ca07bf1ccba4 Mon Sep 17 00:00:00 2001 From: Liphen Date: Sun, 25 Feb 2024 16:53:09 +0800 Subject: [PATCH] =?UTF-8?q?fix(fu):=20=E4=BF=AE=E5=A4=8Dsc=E5=9C=B0?= =?UTF-8?q?=E5=9D=80=E5=89=8D=E9=80=92bug?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/execute/Fu.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala index 7f1addc..e03084b 100644 --- a/chisel/playground/src/pipeline/execute/Fu.scala +++ b/chisel/playground/src/pipeline/execute/Fu.scala @@ -80,7 +80,7 @@ class Fu(implicit val cpuConfig: CpuConfig) extends Module { val mem_addr = Seq.tabulate(cpuConfig.commitNum)(i => Mux( - LSUOpType.isAMO(io.inst(i).info.op) || LSUOpType.isLR(io.inst(i).info.op), + LSUOpType.isAtom(io.inst(i).info.op), io.inst(i).src_info.src1_data, io.inst(i).src_info.src1_data + io.inst(i).info.imm )