diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala
index 7f1addc..e03084b 100644
--- a/chisel/playground/src/pipeline/execute/Fu.scala
+++ b/chisel/playground/src/pipeline/execute/Fu.scala
@@ -80,7 +80,7 @@ class Fu(implicit val cpuConfig: CpuConfig) extends Module {
 
   val mem_addr = Seq.tabulate(cpuConfig.commitNum)(i =>
     Mux(
-      LSUOpType.isAMO(io.inst(i).info.op) || LSUOpType.isLR(io.inst(i).info.op),
+      LSUOpType.isAtom(io.inst(i).info.op),
       io.inst(i).src_info.src1_data,
       io.inst(i).src_info.src1_data + io.inst(i).info.imm
     )