更改CpuConfig
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@ -5,10 +5,12 @@ import cpu.defines.Const._
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case class CpuConfig(
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// 指令集
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val isRV32: Boolean = false, // 是否为RV32
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val hasMExtension: Boolean = true, // 是否有乘除法单元
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val hasAExtension: Boolean = false, // 是否有原子指令
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val isRV32: Boolean = false, // 是否为RV32
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val hasMExtension: Boolean = true, // 是否实现M扩展,即乘除法指令
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val hasZicsrExtension: Boolean = false, // 是否实现Zicsr扩展,即CSR指令
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val hasZifenceiExtension: Boolean = false, // 是否实现Zifencei扩展,即FENCE.I指令
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val hasAExtension: Boolean = false, // 是否实现A扩展,即原子指令
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// 特权模式
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val hasSMode: Boolean = false, // 是否有S模式
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val hasUMode: Boolean = true, // 是否有U模式
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val hasUMode: Boolean = false // 是否有U模式
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)
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@ -58,24 +58,7 @@ object Instructions extends HasInstrType with CoreParameter {
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def DecodeTable = RVIInstr.table ++
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(if (cpuConfig.hasMExtension) RVMInstr.table else Array.empty) ++
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(if (cpuConfig.hasAExtension) RVAInstr.table else Array.empty) ++
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Priviledged.table ++
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RVZicsrInstr.table ++
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RVZifenceiInstr.table
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}
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object AddressSpace extends CoreParameter {
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// (start, size)
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// address out of MMIO will be considered as DRAM
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def mmio = List(
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(0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC
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(0x40000000L, 0x40000000L) // external devices
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)
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def isMMIO(addr: UInt) = mmio
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.map(range => {
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require(isPow2(range._2))
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val bits = log2Up(range._2)
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(addr ^ range._1.U)(PADDR_WID - 1, bits) === 0.U
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})
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.reduce(_ || _)
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(if (cpuConfig.hasUMode) Privileged.table else Array.empty) ++
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(if (cpuConfig.hasZicsrExtension) RVZicsrInstr.table else Array.empty) ++
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(if (cpuConfig.hasZifenceiExtension) RVZifenceiInstr.table else Array.empty)
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}
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@ -3,7 +3,7 @@ package cpu.defines
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import chisel3._
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import chisel3.util._
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object Priviledged extends HasInstrType with CoreParameter {
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object Privileged extends HasInstrType with CoreParameter {
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def ECALL = BitPat("b000000000000_00000_000_00000_1110011")
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def EBREAK = BitPat("b000000000001_00000_000_00000_1110011")
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def MRET = BitPat("b001100000010_00000_000_00000_1110011")
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