From e955c3d580bf3588569f3fcbd6eb6884ba080367 Mon Sep 17 00:00:00 2001 From: Liphen Date: Fri, 22 Mar 2024 23:16:48 +0800 Subject: [PATCH] =?UTF-8?q?=E6=9B=B4=E6=94=B9CpuConfig?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/CpuConfig.scala | 10 ++++---- chisel/playground/src/defines/Const.scala | 23 +++---------------- .../{Priviledged.scala => Privileged.scala} | 2 +- 3 files changed, 10 insertions(+), 25 deletions(-) rename chisel/playground/src/defines/isa/{Priviledged.scala => Privileged.scala} (94%) diff --git a/chisel/playground/src/CpuConfig.scala b/chisel/playground/src/CpuConfig.scala index f1c51bb..113a425 100644 --- a/chisel/playground/src/CpuConfig.scala +++ b/chisel/playground/src/CpuConfig.scala @@ -5,10 +5,12 @@ import cpu.defines.Const._ case class CpuConfig( // 指令集 - val isRV32: Boolean = false, // 是否为RV32 - val hasMExtension: Boolean = true, // 是否有乘除法单元 - val hasAExtension: Boolean = false, // 是否有原子指令 + val isRV32: Boolean = false, // 是否为RV32 + val hasMExtension: Boolean = true, // 是否实现M扩展，即乘除法指令 + val hasZicsrExtension: Boolean = false, // 是否实现Zicsr扩展，即CSR指令 + val hasZifenceiExtension: Boolean = false, // 是否实现Zifencei扩展，即FENCE.I指令 + val hasAExtension: Boolean = false, // 是否实现A扩展，即原子指令 // 特权模式 val hasSMode: Boolean = false, // 是否有S模式 - val hasUMode: Boolean = true, // 是否有U模式 + val hasUMode: Boolean = false // 是否有U模式 ) diff --git a/chisel/playground/src/defines/Const.scala b/chisel/playground/src/defines/Const.scala index 0509631..09f1d61 100644 --- a/chisel/playground/src/defines/Const.scala +++ b/chisel/playground/src/defines/Const.scala @@ -58,24 +58,7 @@ object Instructions extends HasInstrType with CoreParameter { def DecodeTable = RVIInstr.table ++ (if (cpuConfig.hasMExtension) RVMInstr.table else Array.empty) ++ (if (cpuConfig.hasAExtension) RVAInstr.table else Array.empty) ++ - Priviledged.table ++ - RVZicsrInstr.table ++ - RVZifenceiInstr.table -} - -object AddressSpace extends CoreParameter { - // (start, size) - // address out of MMIO will be considered as DRAM - def mmio = List( - (0x30000000L, 0x10000000L), // internal devices, such as CLINT and PLIC - (0x40000000L, 0x40000000L) // external devices - ) - - def isMMIO(addr: UInt) = mmio - .map(range => { - require(isPow2(range._2)) - val bits = log2Up(range._2) - (addr ^ range._1.U)(PADDR_WID - 1, bits) === 0.U - }) - .reduce(_ || _) + (if (cpuConfig.hasUMode) Privileged.table else Array.empty) ++ + (if (cpuConfig.hasZicsrExtension) RVZicsrInstr.table else Array.empty) ++ + (if (cpuConfig.hasZifenceiExtension) RVZifenceiInstr.table else Array.empty) } diff --git a/chisel/playground/src/defines/isa/Priviledged.scala b/chisel/playground/src/defines/isa/Privileged.scala similarity index 94% rename from chisel/playground/src/defines/isa/Priviledged.scala rename to chisel/playground/src/defines/isa/Privileged.scala index 1ed3e5e..5bdc6bc 100644 --- a/chisel/playground/src/defines/isa/Priviledged.scala +++ b/chisel/playground/src/defines/isa/Privileged.scala @@ -3,7 +3,7 @@ package cpu.defines import chisel3._ import chisel3.util._ -object Priviledged extends HasInstrType with CoreParameter { +object Privileged extends HasInstrType with CoreParameter { def ECALL = BitPat("b000000000000_00000_000_00000_1110011") def EBREAK = BitPat("b000000000001_00000_000_00000_1110011") def MRET = BitPat("b001100000010_00000_000_00000_1110011")