feat: 成功生成sram的verilog

2024-03-22 22:57:04 +08:00 · 2024-03-22 22:57:04 +08:00 · 81b3915c46
parent 0a20a7cda9
commit 81b3915c46
1 changed files with 2 additions and 1 deletions
--- a/chisel/playground/src/pipeline/execute/fu/Lsu.scala
+++ b/chisel/playground/src/pipeline/execute/fu/Lsu.scala
@ -120,6 +120,7 @@ class Lsu extends Module {
  io.dataSram.addr  := req_addr
  io.dataSram.wdata := req_wdata

-  val result = Mux(partial_load, rdata_partial_result, rdata_result)
+  val result = Wire(UInt(XLEN.W))
+  result := Mux(partial_load, rdata_partial_result, rdata_result)
  BoringUtils.addSource(result, "lsu_rdata")
 }