diff --git a/chisel/playground/src/pipeline/execute/fu/Lsu.scala b/chisel/playground/src/pipeline/execute/fu/Lsu.scala
index 4e31f57..1b11bf2 100644
--- a/chisel/playground/src/pipeline/execute/fu/Lsu.scala
+++ b/chisel/playground/src/pipeline/execute/fu/Lsu.scala
@@ -120,6 +120,7 @@ class Lsu extends Module {
   io.dataSram.addr  := req_addr
   io.dataSram.wdata := req_wdata
 
-  val result = Mux(partial_load, rdata_partial_result, rdata_result)
+  val result = Wire(UInt(XLEN.W))
+  result := Mux(partial_load, rdata_partial_result, rdata_result)
   BoringUtils.addSource(result, "lsu_rdata")
 }