feat: 升级chisel版本至5.0

chisel/build.sc

@@ -7,7 +7,7 @@ import mill.scalalib.TestModule.ScalaTest
 import mill.bsp._
 
 object playground extends ScalaModule with ScalafmtModule { m =>
-  val useChisel5 = false
+  val useChisel5 = true
   override def scalaVersion = "2.13.10"
   override def scalacOptions = Seq(
     "-language:reflectiveCalls",

chisel/playground/src/Elaborate.scala

@@ -4,11 +4,6 @@ import circt.stage._
 object Elaborate extends App {
   implicit val cpuConfig = new CpuConfig()
   def top                = new PuaCpu()
-  val useMFC             = false // use MLIR-based firrtl compiler
   val generator          = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
-  if (useMFC) {
-    (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
-  } else {
-    (new chisel3.stage.ChiselStage).execute(args, generator)
-  }
+  (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
 }