From 0a20a7cda99caff85c37005af826946e82ba3083 Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Fri, 22 Mar 2024 22:56:41 +0800
Subject: [PATCH] =?UTF-8?q?feat:=20=E5=8D=87=E7=BA=A7chisel=E7=89=88?=
 =?UTF-8?q?=E6=9C=AC=E8=87=B35.0?=
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---
 chisel/build.sc                       | 2 +-
 chisel/playground/src/Elaborate.scala | 7 +------
 2 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/chisel/build.sc b/chisel/build.sc
index 548f0b0..2768db8 100644
--- a/chisel/build.sc
+++ b/chisel/build.sc
@@ -7,7 +7,7 @@ import mill.scalalib.TestModule.ScalaTest
 import mill.bsp._
 
 object playground extends ScalaModule with ScalafmtModule { m =>
-  val useChisel5 = false
+  val useChisel5 = true
   override def scalaVersion = "2.13.10"
   override def scalacOptions = Seq(
     "-language:reflectiveCalls",
diff --git a/chisel/playground/src/Elaborate.scala b/chisel/playground/src/Elaborate.scala
index c102eb2..426187d 100644
--- a/chisel/playground/src/Elaborate.scala
+++ b/chisel/playground/src/Elaborate.scala
@@ -4,11 +4,6 @@ import circt.stage._
 object Elaborate extends App {
   implicit val cpuConfig = new CpuConfig()
   def top                = new PuaCpu()
-  val useMFC             = false // use MLIR-based firrtl compiler
   val generator          = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
-  if (useMFC) {
-    (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
-  } else {
-    (new chisel3.stage.ChiselStage).execute(args, generator)
-  }
+  (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
 }