From 81b3915c46029d58ff703fc73331675e653d0097 Mon Sep 17 00:00:00 2001 From: Liphen Date: Fri, 22 Mar 2024 22:57:04 +0800 Subject: [PATCH] =?UTF-8?q?feat:=20=E6=88=90=E5=8A=9F=E7=94=9F=E6=88=90sra?= =?UTF-8?q?m=E7=9A=84verilog?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/execute/fu/Lsu.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/chisel/playground/src/pipeline/execute/fu/Lsu.scala b/chisel/playground/src/pipeline/execute/fu/Lsu.scala index 4e31f57..1b11bf2 100644 --- a/chisel/playground/src/pipeline/execute/fu/Lsu.scala +++ b/chisel/playground/src/pipeline/execute/fu/Lsu.scala @@ -120,6 +120,7 @@ class Lsu extends Module { io.dataSram.addr := req_addr io.dataSram.wdata := req_wdata - val result = Mux(partial_load, rdata_partial_result, rdata_result) + val result = Wire(UInt(XLEN.W)) + result := Mux(partial_load, rdata_partial_result, rdata_result) BoringUtils.addSource(result, "lsu_rdata") }