fix(csr): stval只在deleg的情况下更新

2024-01-21 13:57:45 +08:00 · 2024-01-21 13:57:45 +08:00 · 2bff20053d
parent 2a09884e0f
commit 2bff20053d
1 changed files with 3 additions and 3 deletions
--- a/chisel/playground/src/pipeline/execute/fu/Csr.scala
+++ b/chisel/playground/src/pipeline/execute/fu/Csr.scala
@ -327,10 +327,10 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {

  when(raise_exception) {
    val tval = mem_ex.tval(exceptionNO)
-    when(mode === ModeM) {
-      mtval := tval
-    }.otherwise {
+    when(delegS) {
      stval := tval
+    }.otherwise {
+      mtval := tval
    }
  }