From 2bff20053d21e6584595aa6c1b2df15f9b493b28 Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Sun, 21 Jan 2024 13:57:45 +0800
Subject: [PATCH] =?UTF-8?q?fix(csr):=20stval=E5=8F=AA=E5=9C=A8deleg?=
 =?UTF-8?q?=E7=9A=84=E6=83=85=E5=86=B5=E4=B8=8B=E6=9B=B4=E6=96=B0?=
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---
 chisel/playground/src/pipeline/execute/fu/Csr.scala | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/chisel/playground/src/pipeline/execute/fu/Csr.scala b/chisel/playground/src/pipeline/execute/fu/Csr.scala
index f08797e..429a1af 100644
--- a/chisel/playground/src/pipeline/execute/fu/Csr.scala
+++ b/chisel/playground/src/pipeline/execute/fu/Csr.scala
@@ -327,10 +327,10 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
 
   when(raise_exception) {
     val tval = mem_ex.tval(exceptionNO)
-    when(mode === ModeM) {
-      mtval := tval
-    }.otherwise {
+    when(delegS) {
       stval := tval
+    }.otherwise {
+      mtval := tval
     }
   }