重构mem unit
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Liphen
parent
7ee50481a9
commit
33e20fa99c
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@ -29,63 +29,42 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
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mou.in.info := io.memoryStage.inst(0).info
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mou.in.pc := io.memoryStage.inst(0).pc
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val mem_sel = VecInit(
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def selectInstField[T <: Data](select: Vec[Bool], fields: Seq[T]): T = {
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require(select.length == fields.length)
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Mux1H(select.zip(fields))
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}
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val lsu_sel = VecInit(
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io.memoryStage.inst(0).info.valid &&
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io.memoryStage.inst(0).info.fusel === FuType.lsu &&
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!HasExcInt(io.memoryStage.inst(0).ex),
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io.memoryStage.inst(1).info.valid &&
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io.memoryStage.inst(1).info.fusel === FuType.lsu &&
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!HasExcInt(io.memoryStage.inst(1).ex) && !HasExcInt(io.memoryStage.inst(0).ex)
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)
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lsu.memoryUnit.in.mem_en := mem_sel.reduce(_ || _)
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lsu.memoryUnit.in.info := MuxCase(
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0.U.asTypeOf(new InstInfo()),
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Seq(
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mem_sel(0) -> io.memoryStage.inst(0).info,
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mem_sel(1) -> io.memoryStage.inst(1).info
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)
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)
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lsu.memoryUnit.in.src_info := MuxCase(
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0.U.asTypeOf(new SrcInfo()),
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Seq(
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mem_sel(0) -> io.memoryStage.inst(0).src_info,
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mem_sel(1) -> io.memoryStage.inst(1).src_info
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)
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)
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lsu.memoryUnit.in.ex := MuxCase(
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0.U.asTypeOf(new ExceptionInfo()),
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Seq(
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mem_sel(0) -> io.memoryStage.inst(0).ex,
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mem_sel(1) -> io.memoryStage.inst(1).ex
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)
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!HasExcInt(io.memoryStage.inst(1).ex) && !HasExcInt(io.memoryStage.inst(0).ex) // 要保证指令0无异常
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)
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lsu.memoryUnit.in.mem_en := lsu_sel.reduce(_ || _)
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lsu.memoryUnit.in.info := selectInstField(lsu_sel, io.memoryStage.inst.map(_.info))
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lsu.memoryUnit.in.src_info := selectInstField(lsu_sel, io.memoryStage.inst.map(_.src_info))
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lsu.memoryUnit.in.ex := selectInstField(lsu_sel, io.memoryStage.inst.map(_.ex))
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lsu.dataMemory <> io.dataMemory
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lsu.memoryUnit.in.allow_to_go := io.ctrl.allow_to_go
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val csr_sel =
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HasExcInt(io.writeBackStage.inst(0).ex) || !HasExcInt(io.writeBackStage.inst(1).ex)
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io.csr.in.pc := MuxCase(
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0.U,
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Seq(
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(io.ctrl.allow_to_go && csr_sel) -> io.memoryStage.inst(0).pc,
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(io.ctrl.allow_to_go && !csr_sel) -> io.memoryStage.inst(1).pc
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)
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)
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io.csr.in.ex := MuxCase(
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0.U.asTypeOf(new ExceptionInfo()),
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Seq(
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(io.ctrl.allow_to_go && csr_sel) -> io.writeBackStage.inst(0).ex,
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(io.ctrl.allow_to_go && !csr_sel) -> io.writeBackStage.inst(1).ex
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)
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)
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io.csr.in.info := MuxCase(
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0.U.asTypeOf(new InstInfo()),
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Seq(
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(io.ctrl.allow_to_go && csr_sel) -> io.memoryStage.inst(0).info,
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(io.ctrl.allow_to_go && !csr_sel) -> io.memoryStage.inst(1).info
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)
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)
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io.csr.in.pc := 0.U
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io.csr.in.ex := 0.U.asTypeOf(new ExceptionInfo())
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io.csr.in.info := 0.U.asTypeOf(new InstInfo())
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def selectInstField[T <: Data](select: Bool, fields: Seq[T]): T = {
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Mux1H(Seq(select -> fields(0), !select -> fields(1)))
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}
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when(io.ctrl.allow_to_go) {
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io.csr.in.pc := selectInstField(csr_sel, io.memoryStage.inst.map(_.pc))
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io.csr.in.ex := selectInstField(csr_sel, io.writeBackStage.inst.map(_.ex))
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io.csr.in.info := selectInstField(csr_sel, io.memoryStage.inst.map(_.info))
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}
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io.csr.in.set_lr := lsu.memoryUnit.out.set_lr && io.ctrl.allow_to_go
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io.csr.in.set_lr_val := lsu.memoryUnit.out.set_lr_val
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@ -93,34 +72,24 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
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lsu.memoryUnit.in.lr := io.csr.out.lr
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lsu.memoryUnit.in.lr_addr := io.csr.out.lr_addr
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io.decodeUnit(0).wen := io.writeBackStage.inst(0).info.reg_wen
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io.decodeUnit(0).waddr := io.writeBackStage.inst(0).info.reg_waddr
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io.decodeUnit(0).wdata := io.writeBackStage.inst(0).rd_info.wdata(io.writeBackStage.inst(0).info.fusel)
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io.decodeUnit(1).wen := io.writeBackStage.inst(1).info.reg_wen
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io.decodeUnit(1).waddr := io.writeBackStage.inst(1).info.reg_waddr
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io.decodeUnit(1).wdata := io.writeBackStage.inst(1).rd_info.wdata(io.writeBackStage.inst(1).info.fusel)
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for (i <- 0 until cpuConfig.commitNum) {
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io.decodeUnit(i).wen := io.writeBackStage.inst(i).info.reg_wen
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io.decodeUnit(i).waddr := io.writeBackStage.inst(i).info.reg_waddr
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io.decodeUnit(i).wdata := io.writeBackStage.inst(i).rd_info.wdata(io.writeBackStage.inst(i).info.fusel)
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io.writeBackStage.inst(0).pc := io.memoryStage.inst(0).pc
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io.writeBackStage.inst(0).info := io.memoryStage.inst(0).info
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io.writeBackStage.inst(0).rd_info.wdata := io.memoryStage.inst(0).rd_info.wdata
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io.writeBackStage.inst(0).rd_info.wdata(FuType.lsu) := lsu.memoryUnit.out.rdata
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io.writeBackStage.inst(0).ex := Mux(
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mem_sel(0),
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lsu.memoryUnit.out.ex,
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io.memoryStage.inst(0).ex
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)
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io.writeBackStage.inst(i).pc := io.memoryStage.inst(i).pc
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io.writeBackStage.inst(i).info := io.memoryStage.inst(i).info
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io.writeBackStage.inst(i).rd_info.wdata := io.memoryStage.inst(i).rd_info.wdata
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io.writeBackStage.inst(i).rd_info.wdata(FuType.lsu) := lsu.memoryUnit.out.rdata
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io.writeBackStage.inst(i).ex := Mux(
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lsu_sel(i),
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lsu.memoryUnit.out.ex,
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io.memoryStage.inst(i).ex
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)
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}
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io.writeBackStage.inst(1).pc := io.memoryStage.inst(1).pc
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io.writeBackStage.inst(1).info := io.memoryStage.inst(1).info
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io.writeBackStage.inst(1).info.valid := io.memoryStage.inst(1).info.valid &&
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!(io.fetchUnit.flush && csr_sel) // 指令0导致flush时，不应该提交指令1
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io.writeBackStage.inst(1).rd_info.wdata := io.memoryStage.inst(1).rd_info.wdata
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io.writeBackStage.inst(1).rd_info.wdata(FuType.lsu) := lsu.memoryUnit.out.rdata
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io.writeBackStage.inst(1).ex := Mux(
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mem_sel(1),
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lsu.memoryUnit.out.ex,
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io.memoryStage.inst(1).ex
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)
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io.ctrl.flush := io.fetchUnit.flush
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io.ctrl.mem_stall := !lsu.memoryUnit.out.ready && lsu.memoryUnit.in.mem_en
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