修改debug信号的wen为commit
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parent
be93752841
commit
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@ -45,7 +45,7 @@ PuaCpu core(
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.io_data_sram_rdata (data_sram_rdata),
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// debug
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.io_debug_wb_pc (debug_pc),
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.io_debug_wb_rf_wen (debug_commit),
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.io_debug_wb_commit (debug_commit),
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.io_debug_wb_rf_wnum (debug_reg_num),
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.io_debug_wb_rf_wdata (debug_wdata)
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);
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@ -105,7 +105,7 @@ class DataSram extends Bundle {
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class DEBUG extends Bundle {
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val wb_pc = Output(UInt(XLEN.W))
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val wb_rf_wen = Output(Bool())
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val wb_commit = Output(Bool())
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val wb_rf_wnum = Output(UInt(REG_ADDR_WID.W))
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val wb_rf_wdata = Output(UInt(XLEN.W))
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}
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@ -24,7 +24,7 @@ class WriteBackUnit extends Module {
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io.regfile.wdata := io.writeBackStage.data.rd_info.wdata(io.writeBackStage.data.info.fusel)
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io.debug.wb_pc := io.writeBackStage.data.pc
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io.debug.wb_rf_wen := io.writeBackStage.data.info.valid && io.ctrl.ctrlSignal.allow_to_go
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io.debug.wb_commit := io.writeBackStage.data.info.valid && io.ctrl.ctrlSignal.allow_to_go
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io.debug.wb_rf_wnum := io.regfile.waddr
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io.debug.wb_rf_wdata := io.regfile.wdata
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}
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2
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2
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@ -1 +1 @@
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Subproject commit 8fb9d90b00e02be2baa7536ffa43fe0a6d6dc7f6
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Subproject commit 34a01787d1c5883684aa2d30144f9793e13759a2
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