From 4a9e3dc05fbf300ac72f2c4949ea99081cc56681 Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Thu, 9 May 2024 19:16:02 +0800
Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9debug=E4=BF=A1=E5=8F=B7?=
 =?UTF-8?q?=E7=9A=84wen=E4=B8=BAcommit?=
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---
 chisel/playground/resources/top_sram_wrapper.v               | 2 +-
 chisel/playground/src/defines/Bundles.scala                  | 2 +-
 chisel/playground/src/pipeline/writeback/WriteBackUnit.scala | 2 +-
 difftest                                                     | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/chisel/playground/resources/top_sram_wrapper.v b/chisel/playground/resources/top_sram_wrapper.v
index 493459d..406e3c4 100644
--- a/chisel/playground/resources/top_sram_wrapper.v
+++ b/chisel/playground/resources/top_sram_wrapper.v
@@ -45,7 +45,7 @@ PuaCpu core(
     .io_data_sram_rdata       (data_sram_rdata),
     // debug
     .io_debug_wb_pc           (debug_pc),
-    .io_debug_wb_rf_wen       (debug_commit),
+    .io_debug_wb_commit       (debug_commit),
     .io_debug_wb_rf_wnum      (debug_reg_num),
     .io_debug_wb_rf_wdata     (debug_wdata)
 );
diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala
index 243cf66..73b25ef 100644
--- a/chisel/playground/src/defines/Bundles.scala
+++ b/chisel/playground/src/defines/Bundles.scala
@@ -105,7 +105,7 @@ class DataSram extends Bundle {
 
 class DEBUG extends Bundle {
   val wb_pc       = Output(UInt(XLEN.W))
-  val wb_rf_wen   = Output(Bool())
+  val wb_commit   = Output(Bool())
   val wb_rf_wnum  = Output(UInt(REG_ADDR_WID.W))
   val wb_rf_wdata = Output(UInt(XLEN.W))
 }
diff --git a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
index 8ebb335..98d7b29 100644
--- a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
+++ b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
@@ -24,7 +24,7 @@ class WriteBackUnit extends Module {
   io.regfile.wdata := io.writeBackStage.data.rd_info.wdata(io.writeBackStage.data.info.fusel)
 
   io.debug.wb_pc       := io.writeBackStage.data.pc
-  io.debug.wb_rf_wen   := io.writeBackStage.data.info.valid && io.ctrl.ctrlSignal.allow_to_go
+  io.debug.wb_commit   := io.writeBackStage.data.info.valid && io.ctrl.ctrlSignal.allow_to_go
   io.debug.wb_rf_wnum  := io.regfile.waddr
   io.debug.wb_rf_wdata := io.regfile.wdata
 }
diff --git a/difftest b/difftest
index 8fb9d90..34a0178 160000
--- a/difftest
+++ b/difftest
@@ -1 +1 @@
-Subproject commit 8fb9d90b00e02be2baa7536ffa43fe0a6d6dc7f6
+Subproject commit 34a01787d1c5883684aa2d30144f9793e13759a2