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修改CpuConfig

This commit is contained in:
Liphen 2024-03-22 15:07:18 +08:00
parent f43763b32c
commit d16b70ea8d
10 changed files with 39 additions and 120 deletions
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50
chisel/playground/src/CpuConfig.scala
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@ -2,59 +2,13 @@ package cpu
import chisel3.util._
import cpu.defines.Const._
import cpu.defines.HasTlbConst
case class CpuConfig(
val build: Boolean = false, // 是否为build模式
// 指令集
val isRV32: Boolean = false, // 是否为RV32
val hasMExtension: Boolean = true, // 是否有乘除法单元
val hasAExtension: Boolean = true, // 是否有原子指令
val hasAExtension: Boolean = false, // 是否有原子指令
// 特权模式
val hasSMode: Boolean = true, // 是否有S模式
val hasSMode: Boolean = false, // 是否有S模式
val hasUMode: Boolean = true, // 是否有U模式
// 模块配置
val hasCommitBuffer: Boolean = false, // 是否有提交缓存
val decoderNum: Int = 2, // 译码级最大解码的指令数，也是同时访问寄存器的指令数
val commitNum: Int = 2, // 同时提交的指令数, 也是最大发射的指令数
val instFetchNum: Int = 2, // iCache取到的指令数量，最大取值为4
val instFifoDepth: Int = 8, // 指令缓存深度
val mulClockNum: Int = 2, // 乘法器的时钟周期数
val divClockNum: Int = 8, // 除法器的时钟周期数
val branchPredictor: String = "adaptive", // adaptive, global
val tlbEntries: Int = 16 // TLB的条目数
)
/* BPU 的配置文件 */
case class BranchPredictorConfig(
val bhtDepth: Int = 5,
val phtDepth: Int = 6)
case class CacheConfig(
cacheType: String = "icache" // icache, dcache
) extends HasTlbConst {
// ==========================================================
// | tag | index | offset |
// | | | bank index | bank offset |
// ==========================================================
val nway = 2 // 路数，目前只支持2路
val nbank = if (cacheType == "icache") (16 / cpuConfig.instFetchNum) else 8 // 每个项目中的bank数
val nindex = if (cacheType == "icache") 64 else 64 // 每路的项目数
val bitsPerBank = // 每个bank的位数
if (cacheType == "icache") INST_WID * cpuConfig.instFetchNum
else XLEN
val bytesPerBank = bitsPerBank / 8 //每个bank中的字节数
val indexWidth = log2Ceil(nindex) // index的位宽
val bankIndexWidth = log2Ceil(nbank) // bank index的位宽
val bankOffsetWidth = log2Ceil(bytesPerBank) // bank offset的位宽
val offsetWidth = bankIndexWidth + bankOffsetWidth // offset的位宽
val tagWidth = PADDR_WID - pageOffsetLen // tag的位宽
require(offsetWidth + indexWidth == pageOffsetLen) // offsetLen是页内偏移的位宽，为简化设计，这里直接保证每路容量等于页大小
require(isPow2(nindex))
require(isPow2(nway))
require(isPow2(nbank))
require(isPow2(bytesPerBank))
require(isPow2(cpuConfig.instFetchNum))
require(cpuConfig.instFetchNum <= 4, "instFetchNum should be less than 4")
require(nbank * nindex * bytesPerBank <= 4 * 1024, "VIPT requires the cache size to be less than 4KB")
}

2
chisel/playground/src/pipeline/decode/ARegfile.scala
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@ -22,7 +22,7 @@ class RegWrite extends Bundle {
val wdata = Output(UInt(XLEN.W))
}
class ARegFile(implicit val cpuConfig: CpuConfig) extends Module {
class ARegFile extends Module {
val io = IO(new Bundle {
val read = Flipped(new Src12Read())
val write = Flipped(new RegWrite())

2
chisel/playground/src/pipeline/decode/DecodeStage.scala
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@ -17,7 +17,7 @@ class FetchUnitDecodeUnit extends IfIdData {
val data = Output(new IfIdData())
}
class DecodeStage(implicit val cpuConfig: CpuConfig) extends Module {
class DecodeStage extends Module {
val io = IO(new Bundle {
val ctrl = Input(new Bundle {
val allow_to_go = Bool()

44
chisel/playground/src/pipeline/execute/ExecuteStage.scala
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@ -4,7 +4,6 @@ import chisel3._
import chisel3.util._
import cpu.defines._
import cpu.defines.Const._
import cpu.{BranchPredictorConfig, CpuConfig}
import cpu.CpuConfig
class IdExeData extends Bundle {
@ -14,47 +13,24 @@ class IdExeData extends Bundle {
val ex = new ExceptionInfo()
}
class JumpBranchData extends Bundle {
val jump_regiser = Bool()
val branch_inst = Bool()
val pred_branch = Bool()
val branch_target = UInt(XLEN.W)
val update_pht_index = UInt(XLEN.W)
class DecodeUnitExecuteUnit extends Bundle {
val data = new IdExeData()
}
class DecodeUnitExecuteUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
val inst = Vec(cpuConfig.commitNum, new IdExeData())
val jump_branch_info = new JumpBranchData()
}
class ExecuteStage(implicit val cpuConfig: CpuConfig) extends Module {
class ExecuteStage extends Module {
val io = IO(new Bundle {
val ctrl = Input(new Bundle {
val allow_to_go = Vec(cpuConfig.decoderNum, Bool())
val clear = Vec(cpuConfig.decoderNum, Bool())
})
val ctrl = Input(new CtrlSignal())
val decodeUnit = Input(new DecodeUnitExecuteUnit())
val executeUnit = Output(new DecodeUnitExecuteUnit())
})
val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new IdExeData())))
val jump_branch_info = RegInit(0.U.asTypeOf(new JumpBranchData()))
val data = RegInit(0.U.asTypeOf(new IdExeData()))
for (i <- 0 until (cpuConfig.commitNum)) {
when(io.ctrl.clear(i)) {
inst(i) := 0.U.asTypeOf(new IdExeData())
}.elsewhen(io.ctrl.allow_to_go(i)) {
inst(i) := io.decodeUnit.inst(i)
}
when(io.ctrl.do_flush) {
data := 0.U.asTypeOf(new IdExeData())
}.elsewhen(io.ctrl.allow_to_go) {
data := io.decodeUnit.data
}
// inst0携带分支预测相关信息
when(io.ctrl.clear(0)) {
jump_branch_info := 0.U.asTypeOf(new JumpBranchData())
}.elsewhen(io.ctrl.allow_to_go(0)) {
jump_branch_info := io.decodeUnit.jump_branch_info
}
io.executeUnit.inst := inst
io.executeUnit.jump_branch_info := jump_branch_info
io.executeUnit.data := data
}

2
chisel/playground/src/pipeline/execute/fu/Div.scala
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@ -6,7 +6,7 @@ import cpu.defines._
import cpu.defines.Const._
import cpu.CpuConfig
class Div(implicit cpuConfig: CpuConfig) extends Module {
class Div extends Module {
val io = IO(new Bundle {
val src1 = Input(UInt(XLEN.W))
val src2 = Input(UInt(XLEN.W))

2
chisel/playground/src/pipeline/execute/fu/Mdu.scala
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@ -6,7 +6,7 @@ import cpu.defines._
import cpu.defines.Const._
import cpu.CpuConfig
class Mdu(implicit cpuConfig: CpuConfig) extends Module {
class Mdu extends Module {
val io = IO(new Bundle {
val info = Input(new Info())
val src_info = Input(new SrcInfo())

2
chisel/playground/src/pipeline/execute/fu/Mul.scala
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@ -6,7 +6,7 @@ import cpu.defines._
import cpu.defines.Const._
import cpu.CpuConfig
class Mul(implicit val cpuConfig: CpuConfig) extends Module {
class Mul extends Module {
val io = IO(new Bundle {
val src1 = Input(UInt((XLEN + 1).W))
val src2 = Input(UInt((XLEN + 1).W))

4
chisel/playground/src/pipeline/fetch/FetchUnit.scala
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@ -28,8 +28,8 @@ class FetchUnit extends Module {
io.instSram.addr := MuxCase(
pc + 4.U,
Seq(
io.execute.flush -> io.execute.target,
!io.ctrl.allow_to_go -> pc
io.execute.flush -> io.execute.target,
!io.ctrl.ctrlSignal.allow_to_go -> pc
)
)

26
chisel/playground/src/pipeline/memory/MemoryStage.scala
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@ -11,31 +11,25 @@ class ExeMemData extends Bundle {
val info = new Info()
val rd_info = new RdInfo()
val src_info = new SrcInfo()
val ex = new ExceptionInfo()
}
class ExecuteUnitMemoryUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
val inst = Vec(cpuConfig.commitNum, new ExeMemData())
class ExecuteUnitMemoryUnit extends Bundle {
val data = new ExeMemData()
}
class MemoryStage(implicit val cpuConfig: CpuConfig) extends Module {
class MemoryStage extends Module {
val io = IO(new Bundle {
val ctrl = Input(new Bundle {
val allow_to_go = Bool()
val clear = Bool()
})
val ctrl = Input(new CtrlSignal())
val executeUnit = Input(new ExecuteUnitMemoryUnit())
val memoryUnit = Output(new ExecuteUnitMemoryUnit())
})
val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new ExeMemData())))
val data = RegInit(0.U.asTypeOf(new ExeMemData()))
for (i <- 0 until (cpuConfig.commitNum)) {
when(io.ctrl.clear) {
inst(i) := 0.U.asTypeOf(new ExeMemData())
}.elsewhen(io.ctrl.allow_to_go) {
inst(i) := io.executeUnit.inst(i)
}
when(io.ctrl.do_flush) {
data := 0.U.asTypeOf(new ExeMemData())
}.elsewhen(io.ctrl.allow_to_go) {
data := io.executeUnit.data
}
io.memoryUnit.inst := inst
io.memoryUnit.data := data
}

25
chisel/playground/src/pipeline/writeback/WriteBackStage.scala
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@ -13,28 +13,23 @@ class MemWbData extends Bundle {
val ex = new ExceptionInfo()
}
class MemoryUnitWriteBackUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
val inst = Vec(cpuConfig.commitNum, new MemWbData())
class MemoryUnitWriteBackUnit extends Bundle {
val data = new MemWbData()
}
class WriteBackStage(implicit val cpuConfig: CpuConfig) extends Module {
class WriteBackStage extends Module {
val io = IO(new Bundle {
val ctrl = Input(new Bundle {
val allow_to_go = Bool()
val clear = Bool()
})
val ctrl = Input(new CtrlSignal())
val memoryUnit = Input(new MemoryUnitWriteBackUnit())
val writeBackUnit = Output(new MemoryUnitWriteBackUnit())
})
val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new MemWbData())))
val data = RegInit(0.U.asTypeOf(new MemWbData()))
for (i <- 0 until (cpuConfig.commitNum)) {
when(io.ctrl.clear) {
inst(i) := 0.U.asTypeOf(new MemWbData())
}.elsewhen(io.ctrl.allow_to_go) {
inst(i) := io.memoryUnit.inst(i)
}
when(io.ctrl.do_flush) {
data := 0.U.asTypeOf(new MemWbData())
}.elsewhen(io.ctrl.allow_to_go) {
data := io.memoryUnit.data
}
io.writeBackUnit.inst := inst
io.writeBackUnit.data := data
}