修改lsu
This commit is contained in:
Liphen
parent
d16b70ea8d
commit
8520961a64
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@ -7,114 +7,44 @@ import cpu.defines._
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import cpu.defines.Const._
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import cpu.pipeline.decode.RegWrite
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import cpu.pipeline.memory.ExecuteUnitMemoryUnit
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import cpu.pipeline.fetch.ExecuteUnitBranchPredictor
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class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module {
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class ExecuteUnit extends Module {
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val io = IO(new Bundle {
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val ctrl = new ExecuteCtrl()
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val executeStage = Input(new DecodeUnitExecuteUnit())
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val csr = Flipped(new CsrExecuteUnit())
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val bpu = new ExecuteUnitBranchPredictor()
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val fetchUnit = Output(new Bundle {
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val flush = Bool()
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val target = UInt(XLEN.W)
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})
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val decodeUnit = new Bundle {
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val forward = Output(
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Vec(
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cpuConfig.commitNum,
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new Bundle {
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val exe = new RegWrite()
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val is_load = Bool()
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}
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)
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new Bundle {
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val exe = new RegWrite()
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val is_load = Bool()
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}
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)
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}
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val memoryStage = Output(new ExecuteUnitMemoryUnit())
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val dataMemory = new Bundle {
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val addr = Output(UInt(XLEN.W))
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}
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val dataSram = new DataSram()
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})
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val valid = io.executeStage.inst.map(_.info.valid && io.ctrl.allow_to_go)
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val fusel = io.executeStage.inst.map(_.info.fusel)
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val valid = io.executeStage.data.info.valid && io.ctrl.ctrlSignal.allow_to_go
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val fusel = io.executeStage.data.info.fusel
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io.ctrl.flush := io.fetchUnit.flush
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for (i <- 0 until (cpuConfig.commitNum)) {
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io.ctrl.inst(i).is_load :=
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io.executeStage.inst(i).info.fusel === FuType.lsu && io.executeStage.inst(i).info.reg_wen
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io.ctrl.inst(i).reg_waddr := io.executeStage.inst(i).info.reg_waddr
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}
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val is_csr = VecInit(
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Seq.tabulate(cpuConfig.commitNum)(i =>
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fusel(i) === FuType.csr && valid(i) && !(HasExcInt(io.executeStage.inst(i).ex))
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)
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)
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io.csr.in.valid := is_csr.asUInt.orR
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def selectInstField[T <: Data](select: Vec[Bool], fields: Seq[T]): T = {
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require(select.length == fields.length)
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Mux1H(select.zip(fields))
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}
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io.csr.in.pc := selectInstField(is_csr, io.executeStage.inst.map(_.pc))
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io.csr.in.info := selectInstField(is_csr, io.executeStage.inst.map(_.info))
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io.csr.in.src_info := selectInstField(is_csr, io.executeStage.inst.map(_.src_info))
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io.csr.in.ex := selectInstField(is_csr, io.executeStage.inst.map(_.ex))
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io.ctrl.data.is_load := fusel === FuType.lsu && LSUOpType.isLoad(io.executeStage.data.info.op)
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io.ctrl.data.reg_waddr := io.executeStage.data.info.reg_waddr
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io.ctrl.flush := valid && fu.ctrl.flush
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io.ctrl.target := fu.ctrl.target
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val fu = Module(new Fu()).io
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fu.ctrl <> io.ctrl.fu
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for (i <- 0 until (cpuConfig.commitNum)) {
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fu.inst(i).pc := io.executeStage.inst(i).pc
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fu.inst(i).info := io.executeStage.inst(i).info
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fu.inst(i).src_info := io.executeStage.inst(i).src_info
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}
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fu.branch.pred_branch := io.executeStage.jump_branch_info.pred_branch
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fu.branch.jump_regiser := io.executeStage.jump_branch_info.jump_regiser
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fu.branch.branch_target := io.executeStage.jump_branch_info.branch_target
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fu.data.pc := io.executeStage.data.pc
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fu.data.info := io.executeStage.data.info
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fu.data.src_info := io.executeStage.data.src_info
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io.dataMemory.addr := fu.dataMemory.addr
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io.memoryStage.data.pc := io.executeStage.data.pc
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io.memoryStage.data.info := io.executeStage.data.info
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io.memoryStage.data.src_info := io.executeStage.data.src_info
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io.memoryStage.data.rd_info := fu.data.rd_info
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io.bpu.pc := io.executeStage.inst(0).pc
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io.bpu.update_pht_index := io.executeStage.jump_branch_info.update_pht_index
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io.bpu.branch := fu.branch.branch
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io.bpu.branch_inst := io.executeStage.jump_branch_info.branch_inst
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io.fetchUnit.flush := valid(0) && io.ctrl.allow_to_go && (fu.branch.flush || io.csr.out.flush)
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io.fetchUnit.target := Mux(io.csr.out.flush, io.csr.out.target, fu.branch.target)
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for (i <- 0 until (cpuConfig.commitNum)) {
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io.memoryStage.inst(i).pc := io.executeStage.inst(i).pc
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io.memoryStage.inst(i).info := io.executeStage.inst(i).info
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io.memoryStage.inst(i).src_info := io.executeStage.inst(i).src_info
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io.memoryStage.inst(i).rd_info.wdata := DontCare
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io.memoryStage.inst(i).rd_info.wdata(FuType.alu) := fu.inst(i).result.alu
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io.memoryStage.inst(i).rd_info.wdata(FuType.bru) := io.executeStage.inst(i).pc + 4.U
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io.memoryStage.inst(i).rd_info.wdata(FuType.mdu) := fu.inst(i).result.mdu
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io.memoryStage.inst(i).rd_info.wdata(FuType.csr) := io.csr.out.rdata
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io.memoryStage.inst(i).ex := Mux(
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(HasExcInt(io.executeStage.inst(i).ex)) && io.executeStage.inst(i).info.valid,
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io.executeStage.inst(i).ex,
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MuxLookup(io.executeStage.inst(i).info.fusel, io.executeStage.inst(i).ex)(
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Seq(
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FuType.csr -> io.csr.out.ex
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)
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)
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)
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io.memoryStage.inst(i).ex.exception(instAddrMisaligned) :=
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io.executeStage.inst(i).ex.exception(instAddrMisaligned) ||
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io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR
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io.memoryStage.inst(i).ex.tval(instAddrMisaligned) := Mux(
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io.executeStage.inst(i).ex.exception(instAddrMisaligned),
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io.executeStage.inst(i).ex.tval(instAddrMisaligned),
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io.fetchUnit.target
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)
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io.decodeUnit.forward(i).exe.wen := io.memoryStage.inst(i).info.reg_wen
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io.decodeUnit.forward(i).exe.waddr := io.memoryStage.inst(i).info.reg_waddr
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io.decodeUnit.forward(i).exe.wdata := io.memoryStage.inst(i).rd_info.wdata(io.memoryStage.inst(i).info.fusel)
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io.decodeUnit.forward(i).is_load := io.ctrl.inst(i).is_load
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}
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// 数据前递
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io.decodeUnit.forward.exe.wen := io.memoryStage.data.info.reg_wen
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io.decodeUnit.forward.exe.waddr := io.memoryStage.data.info.reg_waddr
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io.decodeUnit.forward.exe.wdata := io.memoryStage.data.rd_info.wdata(io.memoryStage.data.info.fusel)
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io.decodeUnit.forward.is_load := io.ctrl.data.is_load
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}
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@ -0,0 +1,125 @@
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package cpu.pipeline.execute
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import chisel3._
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import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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import chisel3.util.experimental.BoringUtils
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class Lsu extends Module {
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val io = IO(new Bundle {
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val info = Input(new Info())
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val src_info = Input(new SrcInfo())
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val dataSram = new DataSram()
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})
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def genWmask(addr: UInt, sizeEncode: UInt): UInt = {
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LookupTree(
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sizeEncode,
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List(
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"b00".U -> 0x1.U, //0001 << addr(2:0)
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"b01".U -> 0x3.U, //0011
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"b10".U -> 0xf.U, //1111
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"b11".U -> 0xff.U //11111111
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)
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) << addr(2, 0)
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}
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def genWdata(data: UInt, sizeEncode: UInt): UInt = {
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LookupTree(
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sizeEncode,
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List(
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"b00".U -> Fill(8, data(7, 0)),
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"b01".U -> Fill(4, data(15, 0)),
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"b10".U -> Fill(2, data(31, 0)),
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"b11".U -> data
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)
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)
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}
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def genWmask32(addr: UInt, sizeEncode: UInt): UInt = {
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LookupTree(
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sizeEncode,
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List(
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"b00".U -> 0x1.U, //0001 << addr(1:0)
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"b01".U -> 0x3.U, //0011
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"b10".U -> 0xf.U //1111
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)
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) << addr(1, 0)
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}
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def genWdata32(data: UInt, sizeEncode: UInt): UInt = {
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LookupTree(
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sizeEncode,
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List(
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"b00".U -> Fill(4, data(7, 0)),
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"b01".U -> Fill(2, data(15, 0)),
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"b10".U -> data
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)
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)
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}
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val valid = io.info.valid && io.info.fusel === FuType.lsu // && 无异常
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val op = io.info.op
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val is_load = valid && LSUOpType.isLoad(op)
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val is_store = valid && LSUOpType.isStore(op)
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val addr = io.src_info.src1_data + io.info.imm
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val wdata = io.src_info.src2_data
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val partial_load = !is_store && (op =/= LSUOpType.ld)
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val size = op(1, 0)
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val req_addr = if (XLEN == 32) SignedExtend(addr, XLEN) else addr
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val req_wdata = if (XLEN == 32) genWdata32(wdata, size) else genWdata(wdata, size)
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val req_wmask = if (XLEN == 32) genWmask32(addr, size) else genWmask(addr, size)
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val rdata = io.dataSram.rdata
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val rdata64 = LookupTree(
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addr(2, 0),
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List(
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"b000".U -> rdata(63, 0),
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"b001".U -> rdata(63, 8),
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"b010".U -> rdata(63, 16),
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"b011".U -> rdata(63, 24),
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"b100".U -> rdata(63, 32),
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"b101".U -> rdata(63, 40),
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"b110".U -> rdata(63, 48),
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"b111".U -> rdata(63, 56)
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)
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)
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val rdata32 = LookupTree(
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addr(1, 0),
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List(
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"b00".U -> rdata(31, 0),
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"b01".U -> rdata(31, 8),
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"b10".U -> rdata(31, 16),
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"b11".U -> rdata(31, 24)
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)
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)
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val rdata_result = if (XLEN == 32) rdata32 else rdata64
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val rdata_partial_result = LookupTree(
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op,
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List(
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LSUOpType.lb -> SignedExtend(rdata_result(7, 0), XLEN),
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LSUOpType.lh -> SignedExtend(rdata_result(15, 0), XLEN),
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LSUOpType.lw -> SignedExtend(rdata_result(31, 0), XLEN),
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LSUOpType.lbu -> ZeroExtend(rdata_result(7, 0), XLEN),
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LSUOpType.lhu -> ZeroExtend(rdata_result(15, 0), XLEN),
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LSUOpType.lwu -> ZeroExtend(rdata_result(31, 0), XLEN)
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)
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)
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val addr_aligned = LookupTree(
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op(1, 0),
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List(
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"b00".U -> true.B, //b
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"b01".U -> (addr(0) === 0.U), //h
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"b10".U -> (addr(1, 0) === 0.U), //w
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"b11".U -> (addr(2, 0) === 0.U) //d
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)
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)
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io.dataSram.en := valid && addr_aligned
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io.dataSram.wen := req_wmask & Fill(8, is_store)
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io.dataSram.addr := req_addr
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io.dataSram.wdata := req_wdata
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val result = Mux(partial_load, rdata_partial_result, rdata_result)
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BoringUtils.addSource(result, "lsu_rdata")
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}
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@ -8,8 +8,9 @@ import cpu.CpuConfig
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import cpu.pipeline.decode.RegWrite
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import cpu.pipeline.execute.CsrMemoryUnit
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import cpu.pipeline.writeback.MemoryUnitWriteBackUnit
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import chisel3.util.experimental.BoringUtils
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class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
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class MemoryUnit extends Module {
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val io = IO(new Bundle {
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val ctrl = new MemoryCtrl()
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val memoryStage = Input(new ExecuteUnitMemoryUnit())
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@ -17,89 +18,20 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
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val flush = Bool()
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val target = UInt(XLEN.W)
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})
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val decodeUnit = Output(Vec(cpuConfig.commitNum, new RegWrite()))
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val csr = Flipped(new CsrMemoryUnit())
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val decodeUnit = Output(new RegWrite())
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val writeBackStage = Output(new MemoryUnitWriteBackUnit())
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val dataMemory = new Lsu_DataMemory()
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val dataSram = new DataSram()
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})
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val lsu = Module(new Lsu()).io
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val mou = Module(new Mou()).io
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val rdata = Wire(UInt(XLEN.W))
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BoringUtils.addSink(rdata, "lsu_rdata")
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mou.in.info := io.memoryStage.inst(0).info
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mou.in.pc := io.memoryStage.inst(0).pc
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io.decodeUnit.wen := io.writeBackStage.data.info.reg_wen
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io.decodeUnit.waddr := io.writeBackStage.data.info.reg_waddr
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io.decodeUnit.wdata := io.writeBackStage.data.rd_info.wdata(io.writeBackStage.data.info.fusel)
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def selectInstField[T <: Data](select: Vec[Bool], fields: Seq[T]): T = {
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require(select.length == fields.length)
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Mux1H(select.zip(fields))
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}
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val lsu_sel = VecInit(
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io.memoryStage.inst(0).info.valid &&
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io.memoryStage.inst(0).info.fusel === FuType.lsu &&
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!HasExcInt(io.memoryStage.inst(0).ex),
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io.memoryStage.inst(1).info.valid &&
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io.memoryStage.inst(1).info.fusel === FuType.lsu &&
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!HasExcInt(io.memoryStage.inst(1).ex) && !HasExcInt(io.memoryStage.inst(0).ex) // 要保证指令0无异常
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)
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lsu.memoryUnit.in.mem_en := lsu_sel.reduce(_ || _)
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lsu.memoryUnit.in.info := selectInstField(lsu_sel, io.memoryStage.inst.map(_.info))
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lsu.memoryUnit.in.src_info := selectInstField(lsu_sel, io.memoryStage.inst.map(_.src_info))
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lsu.memoryUnit.in.ex := selectInstField(lsu_sel, io.memoryStage.inst.map(_.ex))
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lsu.dataMemory <> io.dataMemory
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lsu.memoryUnit.in.allow_to_go := io.ctrl.allow_to_go
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val csr_sel =
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HasExcInt(io.writeBackStage.inst(0).ex) || !HasExcInt(io.writeBackStage.inst(1).ex)
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io.csr.in.pc := 0.U
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io.csr.in.ex := 0.U.asTypeOf(new ExceptionInfo())
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io.csr.in.info := 0.U.asTypeOf(new Info())
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def selectInstField[T <: Data](select: Bool, fields: Seq[T]): T = {
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Mux1H(Seq(select -> fields(0), !select -> fields(1)))
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}
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when(io.ctrl.allow_to_go) {
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io.csr.in.pc := selectInstField(csr_sel, io.memoryStage.inst.map(_.pc))
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io.csr.in.ex := selectInstField(csr_sel, io.writeBackStage.inst.map(_.ex))
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io.csr.in.info := selectInstField(csr_sel, io.memoryStage.inst.map(_.info))
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}
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io.csr.in.lr_wen := lsu.memoryUnit.out.lr_wen && io.ctrl.allow_to_go
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io.csr.in.lr_wbit := lsu.memoryUnit.out.lr_wbit
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io.csr.in.lr_waddr := lsu.memoryUnit.out.lr_waddr
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lsu.memoryUnit.in.lr := io.csr.out.lr
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lsu.memoryUnit.in.lr_addr := io.csr.out.lr_addr
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for (i <- 0 until cpuConfig.commitNum) {
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io.decodeUnit(i).wen := io.writeBackStage.inst(i).info.reg_wen
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io.decodeUnit(i).waddr := io.writeBackStage.inst(i).info.reg_waddr
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io.decodeUnit(i).wdata := io.writeBackStage.inst(i).rd_info.wdata(io.writeBackStage.inst(i).info.fusel)
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io.writeBackStage.inst(i).pc := io.memoryStage.inst(i).pc
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io.writeBackStage.inst(i).info := io.memoryStage.inst(i).info
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io.writeBackStage.inst(i).rd_info.wdata := io.memoryStage.inst(i).rd_info.wdata
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io.writeBackStage.inst(i).rd_info.wdata(FuType.lsu) := lsu.memoryUnit.out.rdata
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io.writeBackStage.inst(i).ex := Mux(
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lsu_sel(i),
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lsu.memoryUnit.out.ex,
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io.memoryStage.inst(i).ex
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)
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}
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io.writeBackStage.inst(1).info.valid := io.memoryStage.inst(1).info.valid &&
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!(io.fetchUnit.flush && csr_sel) // 指令0导致flush时，不应该提交指令1
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io.ctrl.flush := io.fetchUnit.flush
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io.ctrl.mem_stall := !lsu.memoryUnit.out.ready && lsu.memoryUnit.in.mem_en
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io.ctrl.fence_i := mou.out.fence_i
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io.ctrl.complete_single_request := lsu.memoryUnit.out.complete_single_request
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io.ctrl.sfence_vma.valid := mou.out.sfence_vma
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io.ctrl.sfence_vma.src_info := io.memoryStage.inst(0).src_info
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io.fetchUnit.flush := io.ctrl.allow_to_go && (io.csr.out.flush || mou.out.flush)
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io.fetchUnit.target := Mux(io.csr.out.flush, io.csr.out.target, mou.out.target)
|
||||
io.writeBackStage.data.pc := io.memoryStage.data.pc
|
||||
io.writeBackStage.data.info := io.memoryStage.data.info
|
||||
io.writeBackStage.data.rd_info.wdata := io.memoryStage.data.rd_info.wdata
|
||||
io.writeBackStage.data.rd_info.wdata(FuType.lsu) := rdata
|
||||
}
|
||||
|
|
|
|||
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Reference in New Issue