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删去部分无用定义

This commit is contained in:
Liphen 2024-03-11 19:46:55 +08:00
parent aaf97820d4
commit 32005bb3e2
2 changed files with 3 additions and 25 deletions
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24
chisel/playground/src/defines/isa/Instructions.scala
View File

@ -11,10 +11,9 @@ trait HasInstrType {
def InstrB = "b0001".U
def InstrU = "b0110".U
def InstrJ = "b0111".U
def InstrA = "b1110".U
def InstrSA = "b1111".U // Atom Inst: SC
def isrfWen(instrType: UInt): Bool = instrType(2)
def isRegWen(instrType: UInt): Bool = instrType(2)
}
object SrcType {
@ -39,16 +38,6 @@ object FuOpType {
def apply() = UInt(7.W)
}
// BTB
object BTBtype {
def B = "b00".U // branch
def J = "b01".U // jump
def I = "b10".U // indirect
def R = "b11".U // return
def apply() = UInt(2.W)
}
// ALU
object ALUOpType {
def add = "b100000".U
@ -122,12 +111,6 @@ object LSUOpType { //TODO: refactor LSU fuop
def isLR(func: UInt): Bool = func === lr
def isSC(func: UInt): Bool = func === sc
def isAMO(func: UInt): Bool = isAtom(func) && !isLR(func) && !isSC(func)
def needMemRead(func: UInt): Bool = isLoad(func) || isAMO(func) || isLR(func)
def needMemWrite(func: UInt): Bool = isStore(func) || isAMO(func) || isSC(func)
def atomW = "010".U
def atomD = "011".U
}
// memory order unit
@ -257,11 +240,6 @@ trait HasCSRConst {
val Tdata1 = 0x7a1
// Debug Mode Registers (not implemented)
def privEcall = 0x000.U
def privEbreak = 0x001.U
def privMret = 0x302.U
def privSret = 0x102.U
def ModeM = 0x3.U
def ModeH = 0x2.U
def ModeS = 0x1.U

4
chisel/playground/src/pipeline/decode/Decoder.scala
View File

@ -45,8 +45,8 @@ class Decoder extends Module with HasInstrType with HasCSRConst {
io.out.info.src2_raddr := Mux(io.out.info.src2_ren, rt, 0.U)
io.out.info.fusel := fuType
io.out.info.op := fuOpType
io.out.info.reg_wen := isrfWen(instrType)
io.out.info.reg_waddr := Mux(isrfWen(instrType), rd, 0.U)
io.out.info.reg_wen := isRegWen(instrType)
io.out.info.reg_waddr := Mux(isRegWen(instrType), rd, 0.U)
io.out.info.imm := LookupTree(
instrType,
Seq(