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refactor(csr): 修改特权指令的解码赋值

This commit is contained in:
Liphen 2024-03-11 19:26:26 +08:00
parent 194e8c90d5
commit 68dd1be7ac
10 changed files with 66 additions and 54 deletions
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1
chisel/playground/src/defines/Bundles.scala
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@ -42,7 +42,6 @@ class Info extends Bundle {
val reg_waddr = UInt(REG_ADDR_WID.W)
val imm = UInt(XLEN.W)
val inst = UInt(XLEN.W)
val ret = Vec(RetType.num, Bool())
}
class MemRead extends Bundle {

2
chisel/playground/src/defines/Const.scala
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@ -54,7 +54,7 @@ object Const extends Constants with AXIConst with HasExceptionNO
object Instructions extends HasInstrType with CoreParameter {
def NOP = 0x00000013.U
val DecodeDefault = List(InstrN, FuType.csr, CSROpType.jmp)
val DecodeDefault = List(InstrN, FuType.alu, ALUOpType.add)
def DecodeTable = RVIInstr.table ++
(if (cpuConfig.hasMExtension) RVMInstr.table else Array.empty) ++
(if (cpuConfig.hasAExtension) RVAInstr.table else Array.empty) ++

18
chisel/playground/src/defines/Util.scala
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@ -9,6 +9,24 @@ object HasExcInt {
}
}
object IsMret {
def apply(info: Info) = {
info.fusel === FuType.csr && info.op === CSROpType.mret
}
}
object IsSret {
def apply(info: Info) = {
info.fusel === FuType.csr && info.op === CSROpType.sret
}
}
object HasRet {
def apply(info: Info) = {
IsMret(info) || IsSret(info)
}
}
object SignedExtend {
def apply(a: UInt, len: Int) = {
val aLen = a.getWidth

26
chisel/playground/src/defines/isa/Instructions.scala
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@ -161,20 +161,19 @@ object MDUOpType {
// csr unit
object CSROpType {
def jmp = "b000".U
def wrt = "b001".U
def set = "b010".U
def clr = "b011".U
def wrti = "b101".U
def seti = "b110".U
def clri = "b111".U
}
def csrrw = "b0001".U
def csrrs = "b0010".U
def csrrc = "b0011".U
def csrrwi = "b0101".U
def csrrsi = "b0110".U
def csrrci = "b0111".U
object RetType {
def uret = 0.U
def sret = 1.U
def mret = 2.U
def num = 3
def ecall = "b1000".U
def ebreak = "b1001".U
def mret = "b1010".U
def sret = "b1011".U
def isCSROp(op: UInt) = !op(3)
}
trait HasCSRConst {
@ -262,7 +261,6 @@ trait HasCSRConst {
def privEbreak = 0x001.U
def privMret = 0x302.U
def privSret = 0x102.U
def privUret = 0x002.U
def ModeM = 0x3.U
def ModeH = 0x2.U

8
chisel/playground/src/defines/isa/Priviledged.scala
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@ -13,14 +13,14 @@ object Priviledged extends HasInstrType with CoreParameter {
def WFI = BitPat("b0001000_00101_00000_000_00000_1110011")
val table_s = Array(
SRET -> List(InstrI, FuType.csr, CSROpType.jmp),
SRET -> List(InstrI, FuType.csr, CSROpType.sret),
SFANCE_VMA -> List(InstrR, FuType.mou, MOUOpType.sfence_vma)
)
val table = Array(
ECALL -> List(InstrI, FuType.csr, CSROpType.jmp),
EBREAK -> List(InstrI, FuType.csr, CSROpType.jmp),
MRET -> List(InstrI, FuType.csr, CSROpType.jmp),
ECALL -> List(InstrI, FuType.csr, CSROpType.ecall),
EBREAK -> List(InstrI, FuType.csr, CSROpType.ebreak),
MRET -> List(InstrI, FuType.csr, CSROpType.mret),
FENCE -> List(InstrS, FuType.mou, MOUOpType.fence), // nop InstrS -> !wen
WFI -> List(InstrI, FuType.alu, ALUOpType.add) // nop rd = x0
) ++ (if (cpuConfig.hasSMode) table_s else Array.empty)

12
chisel/playground/src/defines/isa/RVZicsr.scala
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@ -12,11 +12,11 @@ object RVZicsrInstr extends HasInstrType {
def CSRRCI = BitPat("b????????????_?????_111_?????_1110011")
val table = Array(
CSRRW -> List(InstrI, FuType.csr, CSROpType.wrt),
CSRRS -> List(InstrI, FuType.csr, CSROpType.set),
CSRRC -> List(InstrI, FuType.csr, CSROpType.clr),
CSRRWI -> List(InstrI, FuType.csr, CSROpType.wrti),
CSRRSI -> List(InstrI, FuType.csr, CSROpType.seti),
CSRRCI -> List(InstrI, FuType.csr, CSROpType.clri)
CSRRW -> List(InstrI, FuType.csr, CSROpType.csrrw),
CSRRS -> List(InstrI, FuType.csr, CSROpType.csrrs),
CSRRC -> List(InstrI, FuType.csr, CSROpType.csrrc),
CSRRWI -> List(InstrI, FuType.csr, CSROpType.csrrwi),
CSRRSI -> List(InstrI, FuType.csr, CSROpType.csrrsi),
CSRRCI -> List(InstrI, FuType.csr, CSROpType.csrrci)
)
}

16
chisel/playground/src/pipeline/decode/DecodeUnit.scala
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@ -131,14 +131,14 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep
io.executeStage.inst(i).ex.exception(instrPageFault) := io.instFifo.inst(i).page_fault
io.executeStage.inst(i).ex.exception(instrAddrMisaligned) := io.instFifo.inst(i).addr_misaligned ||
io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch
io.executeStage.inst(i).ex.exception(breakPoint) := info(i).inst(31, 20) === privEbreak &&
info(i).op === CSROpType.jmp && info(i).fusel === FuType.csr
io.executeStage.inst(i).ex.exception(ecallM) := info(i).inst(31, 20) === privEcall &&
info(i).op === CSROpType.jmp && mode === ModeM && info(i).fusel === FuType.csr
io.executeStage.inst(i).ex.exception(ecallS) := info(i).inst(31, 20) === privEcall &&
info(i).op === CSROpType.jmp && mode === ModeS && info(i).fusel === FuType.csr
io.executeStage.inst(i).ex.exception(ecallU) := info(i).inst(31, 20) === privEcall &&
info(i).op === CSROpType.jmp && mode === ModeU && info(i).fusel === FuType.csr
io.executeStage.inst(i).ex.exception(breakPoint) :=
info(i).op === CSROpType.ebreak && info(i).fusel === FuType.csr
io.executeStage.inst(i).ex.exception(ecallM) :=
info(i).op === CSROpType.ecall && mode === ModeM && info(i).fusel === FuType.csr
io.executeStage.inst(i).ex.exception(ecallS) :=
info(i).op === CSROpType.ecall && mode === ModeS && info(i).fusel === FuType.csr
io.executeStage.inst(i).ex.exception(ecallU) :=
info(i).op === CSROpType.ecall && mode === ModeU && info(i).fusel === FuType.csr
io.executeStage.inst(i).ex.tval.map(_ := DontCare)
io.executeStage.inst(i).ex.tval(instrPageFault) := pc(i)
io.executeStage.inst(i).ex.tval(instrAccessFault) := pc(i)

3
chisel/playground/src/pipeline/decode/Decoder.scala
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@ -58,7 +58,4 @@ class Decoder extends Module with HasInstrType with HasCSRConst {
InstrJ -> SignedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN)
)
)
io.out.info.ret(RetType.uret) := inst(31, 20) === privUret && fuOpType === CSROpType.jmp && fuType === FuType.csr
io.out.info.ret(RetType.sret) := inst(31, 20) === privSret && fuOpType === CSROpType.jmp && fuType === FuType.csr
io.out.info.ret(RetType.mret) := inst(31, 20) === privMret && fuOpType === CSROpType.jmp && fuType === FuType.csr
}

4
chisel/playground/src/pipeline/decode/Issue.scala
View File

@ -58,12 +58,12 @@ class Issue(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
// 写satp指令会导致流水线清空
val write_satp = VecInit(
Seq.tabulate(cpuConfig.commitNum)(i =>
inst(i).fusel === FuType.csr && inst(i).op =/= CSROpType.jmp && inst(i).inst(31, 20) === Satp.U
inst(i).fusel === FuType.csr && CSROpType.isCSROp(inst(i).op) && inst(i).inst(31, 20) === Satp.U
)
).asUInt.orR
// uret、sret、mret指令会导致流水线清空
val ret = inst(0).ret.asUInt.orR || inst(1).ret.asUInt.orR
val ret = HasRet(inst(0)) || HasRet(inst(1))
// 这些csr相关指令会导致流水线清空
val is_some_csr_inst = write_satp || ret

30
chisel/playground/src/pipeline/execute/fu/Csr.scala
View File

@ -279,18 +279,19 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
wdata := LookupTree(
op,
List(
CSROpType.wrt -> src1,
CSROpType.set -> (rdata | src1),
CSROpType.clr -> (rdata & ~src1),
CSROpType.wrti -> csri,
CSROpType.seti -> (rdata | csri),
CSROpType.clri -> (rdata & ~csri)
CSROpType.csrrw -> src1,
CSROpType.csrrs -> (rdata | src1),
CSROpType.csrrc -> (rdata & ~src1),
CSROpType.csrrwi -> csri,
CSROpType.csrrsi -> (rdata | csri),
CSROpType.csrrci -> (rdata & ~csri)
)
)
val satp_legal = (wdata.asTypeOf(new Satp()).mode === 0.U) || (wdata.asTypeOf(new Satp()).mode === 8.U)
val write = (valid && op =/= CSROpType.jmp) && (addr =/= Satp.U || satp_legal)
val only_read = VecInit(CSROpType.set, CSROpType.seti, CSROpType.clr, CSROpType.clri).contains(op) && src1 === 0.U
val satp_legal = (wdata.asTypeOf(new Satp()).mode === 0.U) || (wdata.asTypeOf(new Satp()).mode === 8.U)
val write = (valid && CSROpType.isCSROp(op)) && (addr =/= Satp.U || satp_legal)
val only_read =
VecInit(CSROpType.csrrs, CSROpType.csrrsi, CSROpType.csrrc, CSROpType.csrrci).contains(op) && src1 === 0.U
val illegal_mode = mode < addr(9, 8)
val illegal_write = write && (addr(11, 10) === "b11".U) && !only_read
val illegal_access = illegal_mode || illegal_write
@ -308,10 +309,9 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
// CSR inst decode
val ret = Wire(Bool())
val isMret = mem_inst_info.ret(RetType.mret) && mem_valid
val isSret = mem_inst_info.ret(RetType.sret) && mem_valid
val isUret = mem_inst_info.ret(RetType.uret) && mem_valid
ret := isMret || isSret || isUret
val isMret = IsMret(mem_inst_info) && mem_valid
val isSret = IsSret(mem_inst_info) && mem_valid
ret := isMret || isSret
val exceptionNO = ExcPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(mem_ex.exception(i), i.U, sum))
val interruptNO = IntPriority.foldRight(0.U)((i: Int, sum: UInt) => Mux(mem_ex.interrupt(i), i.U, sum))
@ -370,7 +370,7 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
when(isMret) {
val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus))
when(mstatusOld.mpp =/= ModeM){
when(mstatusOld.mpp =/= ModeM) {
mstatusNew.mprv := false.B
}
mstatusNew.ie.m := mstatusOld.pie.m
@ -385,7 +385,7 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
when(isSret) {
val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus))
when(mstatusOld.spp =/= ModeM){
when(mstatusOld.spp =/= ModeM) {
mstatusNew.mprv := false.B
}
mstatusNew.ie.s := mstatusOld.pie.s