Commit Graph

322 Commits

Author SHA1 Message Date
Liphen ca1a6abe7b 修复mem被阻塞时读数据错误问题 2024-05-11 14:49:38 +08:00
Liphen 5bd7124535 feat(debug): 增加sram差分测试接口 2024-05-11 11:40:26 +08:00
Liphen 4a9e3dc05f 修改debug信号的wen为commit 2024-05-09 19:16:02 +08:00
Liphen be93752841 修复jalr指令跳转目标问题 2024-05-08 20:44:30 +08:00
Liphen 4f32948d0b 修复访存级的冲刷问题 2024-05-08 20:01:21 +08:00
Liphen ed586e41b6 fix: Fix FetchUnit PC initialization issue 2024-05-08 16:56:28 +08:00
Liphen 9862402688 fix: Fix FetchUnit PC initialization issue 2024-05-08 13:04:57 +08:00
Liphen 59dc2337cb chore: Update Chisel dependencies to use version 6.1.0 2024-05-07 10:33:44 +08:00
Clo91eaf 18f71c12d4 unuse chisel test 2024-05-07 01:47:10 +08:00
Liphen 333ced6e19 fix(if): 修复第一个pc初始值问题 2024-05-06 16:05:40 +08:00
Liphen f6e8eeb381 Merge branch 'sram' of github.com:Ciliphen/DC-CA-SA-Lab into sram 2024-05-06 15:55:59 +08:00
Liphen 16043c72a0 更新项目结构 2024-05-06 15:54:28 +08:00
Clo91eaf 994f110808 add chisel6 option 2024-04-29 17:15:38 +08:00
Liphen e03e7917db 增加firtool 2024-04-02 12:18:19 +08:00
Liphen 64336aaf1c refactor: 将ex信息在执行级后省略 2024-03-22 23:29:02 +08:00
Liphen be91a70924 修改TestMain 2024-03-22 23:18:11 +08:00
Liphen e955c3d580 更改CpuConfig 2024-03-22 23:16:48 +08:00
Liphen 81b3915c46 feat: 成功生成sram的verilog 2024-03-22 22:57:04 +08:00
Liphen 0a20a7cda9 feat: 升级chisel版本至5.0 2024-03-22 22:56:41 +08:00
Liphen 6508b72858 修改包名,修改各单元逻辑 2024-03-22 22:45:48 +08:00
Liphen 703cd0b41c 修改wb 2024-03-22 21:14:19 +08:00
Liphen 8520961a64 修改lsu 2024-03-22 21:11:58 +08:00
Liphen d16b70ea8d 修改CpuConfig 2024-03-22 15:07:18 +08:00
Liphen f43763b32c 修改bru,去除分支预测 2024-03-22 15:00:13 +08:00
Liphen e6decd7c82 修改mdu 2024-03-22 14:26:21 +08:00
Liphen 1ab2644cba 修改if级逻辑 2024-03-22 14:23:37 +08:00
Liphen a69e4e907d 删除不必要的文件 2024-03-22 14:23:12 +08:00
Liphen 7e13a02cb4 修改id级逻辑 2024-03-22 14:18:56 +08:00
Liphen 2c7af2ce4b 增加sram的顶层接口 2024-03-22 11:13:19 +08:00
Clo91eaf 6274a62ba0 remove .vscode from git. 2024-03-15 00:42:14 +08:00
Liphen b782293dac refactor: 修改异常变量名称 2024-03-11 20:03:33 +08:00
Liphen 32005bb3e2 删去部分无用定义 2024-03-11 19:46:55 +08:00
Liphen aaf97820d4 fix(csr): 修复mem级valid无效时仍使用ex信息 2024-03-11 19:27:23 +08:00
Liphen 68dd1be7ac refactor(csr): 修改特权指令的解码赋值 2024-03-11 19:26:26 +08:00
Liphen 194e8c90d5 docs: 修改README 2024-03-11 18:21:30 +08:00
Liphen 4fddbe5a3d refactor: 迁出文档 2024-03-10 14:44:32 +08:00
Liphen f7fb3c4677 fix(icache): 当地址未对齐时不应访存 2024-03-09 16:12:56 +08:00
Liphen 5e7a2eb162 fix(csr): 在某些条件下重置mprv 2024-03-08 17:28:01 +08:00
Liphen d3a435ac34 修改makefile和文件结构 2024-03-01 14:07:00 +08:00
Liphen 0e17de8d1e refactor: 移动difftest位置 2024-03-01 13:53:01 +08:00
Liphen 4381a93cce docs: 增加csr实验 2024-03-01 12:56:01 +08:00
Liphen 51189b0d38 fix(csr): 修改mip掩码 2024-03-01 12:55:44 +08:00
Liphen eea1f39ef3 docs: 模板更新 2024-02-29 14:38:26 +08:00
Liphen 2f3432acac docs: 增加数据前递实验 2024-02-26 13:17:08 +08:00
Liphen 3999734093 docs: 完成气泡流水线指导手册 2024-02-25 20:00:55 +08:00
Liphen fdc8c2b11e refactor(core): 修改clear信号,使逻辑更清晰 2024-02-25 17:09:12 +08:00
Liphen 3b06ee4f55 fix(fu): 修复sc地址前递bug 2024-02-25 16:53:09 +08:00
Liphen 59db6ed7cd fix(ctrl): 删除无用信号 2024-02-25 16:06:27 +08:00
Liphen 78d0912fb2 修改doc目录 2024-02-25 16:02:28 +08:00
Liphen bf6088d9f7 docs: 增加访存指令理想实验,修改模板 2024-02-20 20:07:04 +08:00