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修改TestMain

This commit is contained in:
Liphen 2024-03-22 23:18:11 +08:00
parent e955c3d580
commit be91a70924
1 changed files with 4 additions and 9 deletions
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13
chisel/playground/test/src/TestMain.scala
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@ -2,13 +2,8 @@
// import circt.stage._
// object TestMain extends App {
// implicit val cpuConfig = new CpuConfig()
// def top = new Top()
// val useMFC = false // use MLIR-based firrtl compiler
// val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
// if (useMFC) {
// (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
// } else {
// (new chisel3.stage.ChiselStage).execute(args, generator)
// }
// implicit val cpuConfig = new CpuConfig()
// def top = new Top()
// val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
// (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
// }