diff --git a/chisel/playground/test/src/TestMain.scala b/chisel/playground/test/src/TestMain.scala
index 9f3f99f..37363ee 100644
--- a/chisel/playground/test/src/TestMain.scala
+++ b/chisel/playground/test/src/TestMain.scala
@@ -2,13 +2,8 @@
 // import circt.stage._
 
 // object TestMain extends App {
-//   implicit val cpuConfig       = new CpuConfig()
-//   def top                   = new Top()
-//   val useMFC                = false // use MLIR-based firrtl compiler
-//   val generator             = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
-//   if (useMFC) {
-//     (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
-//   } else {
-//     (new chisel3.stage.ChiselStage).execute(args, generator)
-//   }
+//   implicit val cpuConfig = new CpuConfig()
+//   def top                = new Top()
+//   val generator          = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
+//   (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
 // }