From be91a70924b1fabc7ba5738b0e32ddca5d5af017 Mon Sep 17 00:00:00 2001 From: Liphen Date: Fri, 22 Mar 2024 23:18:11 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9TestMain?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/test/src/TestMain.scala | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/chisel/playground/test/src/TestMain.scala b/chisel/playground/test/src/TestMain.scala index 9f3f99f..37363ee 100644 --- a/chisel/playground/test/src/TestMain.scala +++ b/chisel/playground/test/src/TestMain.scala @@ -2,13 +2,8 @@ // import circt.stage._ // object TestMain extends App { -// implicit val cpuConfig = new CpuConfig() -// def top = new Top() -// val useMFC = false // use MLIR-based firrtl compiler -// val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) -// if (useMFC) { -// (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog)) -// } else { -// (new chisel3.stage.ChiselStage).execute(args, generator) -// } +// implicit val cpuConfig = new CpuConfig() +// def top = new Top() +// val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) +// (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog)) // }