修改wb
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8520961a64
commit
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@ -11,6 +11,7 @@ class ExeMemData extends Bundle {
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val info = new Info()
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val rd_info = new RdInfo()
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val src_info = new SrcInfo()
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val ex = new ExceptionInfo()
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}
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class ExecuteUnitMemoryUnit extends Bundle {
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@ -19,7 +20,7 @@ class ExecuteUnitMemoryUnit extends Bundle {
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class MemoryStage extends Module {
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val io = IO(new Bundle {
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val ctrl = Input(new CtrlSignal())
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val ctrl = Input(new CtrlSignal())
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val executeUnit = Input(new ExecuteUnitMemoryUnit())
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val memoryUnit = Output(new ExecuteUnitMemoryUnit())
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})
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@ -34,4 +34,5 @@ class MemoryUnit extends Module {
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io.writeBackStage.data.info := io.memoryStage.data.info
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io.writeBackStage.data.rd_info.wdata := io.memoryStage.data.rd_info.wdata
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io.writeBackStage.data.rd_info.wdata(FuType.lsu) := rdata
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io.writeBackStage.data.ex := io.memoryStage.data.ex
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}
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@ -7,69 +7,25 @@ import cpu.defines.Const._
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import cpu.pipeline.decode.RegWrite
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import cpu.CpuConfig
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class WriteBackUnit(implicit val cpuConfig: CpuConfig) extends Module {
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class WriteBackUnit extends Module {
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val io = IO(new Bundle {
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val ctrl = new WriteBackCtrl()
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val writeBackStage = Input(new MemoryUnitWriteBackUnit())
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val regfile = Output(Vec(cpuConfig.commitNum, new RegWrite()))
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val regfile = Output(new RegWrite())
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val debug = new DEBUG()
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})
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io.regfile(0).wen :=
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io.writeBackStage.inst(0).info.valid &&
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io.writeBackStage.inst(0).info.reg_wen &&
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io.ctrl.allow_to_go &&
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!(HasExcInt(io.writeBackStage.inst(0).ex))
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io.regfile.wen :=
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io.writeBackStage.data.info.valid &&
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io.ctrl.ctrlSignal.allow_to_go &&
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io.writeBackStage.data.info.reg_wen &&
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!(HasExcInt(io.writeBackStage.data.ex))
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io.regfile(1).wen :=
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io.writeBackStage.inst(1).info.valid &&
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io.writeBackStage.inst(1).info.reg_wen &&
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io.ctrl.allow_to_go &&
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!(HasExcInt(io.writeBackStage.inst(0).ex)) &&
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!(HasExcInt(io.writeBackStage.inst(1).ex))
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io.regfile.waddr := io.writeBackStage.data.info.reg_waddr
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io.regfile.wdata := io.writeBackStage.data.rd_info.wdata(io.writeBackStage.data.info.fusel)
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for (i <- 0 until (cpuConfig.commitNum)) {
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io.regfile(i).waddr := io.writeBackStage.inst(i).info.reg_waddr
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io.regfile(i).wdata := io.writeBackStage.inst(i).rd_info.wdata(io.writeBackStage.inst(i).info.fusel)
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}
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if (cpuConfig.hasCommitBuffer) {
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val buffer = Module(new CommitBuffer()).io
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for (i <- 0 until (cpuConfig.commitNum)) {
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buffer.enq(i).wb_pc := io.writeBackStage.inst(i).pc
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buffer.enq(i).wb_rf_wen := io.writeBackStage.inst(i).info.valid && io.ctrl.allow_to_go
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buffer.enq(i).wb_rf_wnum := io.regfile(i).waddr
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buffer.enq(i).wb_rf_wdata := io.regfile(i).wdata
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}
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buffer.flush := io.ctrl.do_flush
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io.debug.wb_pc := buffer.deq.wb_pc
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io.debug.wb_rf_wen := buffer.deq.wb_rf_wen
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io.debug.wb_rf_wnum := buffer.deq.wb_rf_wnum
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io.debug.wb_rf_wdata := buffer.deq.wb_rf_wdata
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} else {
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io.debug.wb_pc := Mux(
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clock.asBool,
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io.writeBackStage.inst(0).pc,
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Mux(
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!(io.writeBackStage.inst(1).info.valid && io.ctrl.allow_to_go),
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0.U,
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io.writeBackStage.inst(1).pc
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)
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)
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io.debug.wb_rf_wen := Mux(
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clock.asBool,
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io.writeBackStage.inst(0).info.valid && io.ctrl.allow_to_go,
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io.writeBackStage.inst(1).info.valid && io.ctrl.allow_to_go
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)
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io.debug.wb_rf_wnum := Mux(
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clock.asBool,
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io.regfile(0).waddr,
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io.regfile(1).waddr
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)
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io.debug.wb_rf_wdata := Mux(
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clock.asBool,
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io.regfile(0).wdata,
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io.regfile(1).wdata
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)
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}
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io.debug.wb_pc := io.writeBackStage.data.pc
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io.debug.wb_rf_wen := io.writeBackStage.data.info.valid && io.ctrl.ctrlSignal.allow_to_go
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io.debug.wb_rf_wnum := io.regfile.waddr
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io.debug.wb_rf_wdata := io.regfile.wdata
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}
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