diff --git a/chisel/playground/src/pipeline/memory/MemoryStage.scala b/chisel/playground/src/pipeline/memory/MemoryStage.scala
index ebbdc3b..3872193 100644
--- a/chisel/playground/src/pipeline/memory/MemoryStage.scala
+++ b/chisel/playground/src/pipeline/memory/MemoryStage.scala
@@ -11,6 +11,7 @@ class ExeMemData extends Bundle {
   val info     = new Info()
   val rd_info  = new RdInfo()
   val src_info = new SrcInfo()
+  val ex       = new ExceptionInfo()
 }
 
 class ExecuteUnitMemoryUnit extends Bundle {
@@ -19,7 +20,7 @@ class ExecuteUnitMemoryUnit extends Bundle {
 
 class MemoryStage extends Module {
   val io = IO(new Bundle {
-    val ctrl = Input(new CtrlSignal())
+    val ctrl        = Input(new CtrlSignal())
     val executeUnit = Input(new ExecuteUnitMemoryUnit())
     val memoryUnit  = Output(new ExecuteUnitMemoryUnit())
   })
diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
index 33a7ba5..272f4ff 100644
--- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala
+++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
@@ -34,4 +34,5 @@ class MemoryUnit extends Module {
   io.writeBackStage.data.info                      := io.memoryStage.data.info
   io.writeBackStage.data.rd_info.wdata             := io.memoryStage.data.rd_info.wdata
   io.writeBackStage.data.rd_info.wdata(FuType.lsu) := rdata
+  io.writeBackStage.data.ex                        := io.memoryStage.data.ex
 }
diff --git a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
index 3792f4d..03d0889 100644
--- a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
+++ b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
@@ -7,69 +7,25 @@ import cpu.defines.Const._
 import cpu.pipeline.decode.RegWrite
 import cpu.CpuConfig
 
-class WriteBackUnit(implicit val cpuConfig: CpuConfig) extends Module {
+class WriteBackUnit extends Module {
   val io = IO(new Bundle {
     val ctrl           = new WriteBackCtrl()
     val writeBackStage = Input(new MemoryUnitWriteBackUnit())
-    val regfile        = Output(Vec(cpuConfig.commitNum, new RegWrite()))
+    val regfile        = Output(new RegWrite())
     val debug          = new DEBUG()
   })
 
-  io.regfile(0).wen :=
-    io.writeBackStage.inst(0).info.valid &&
-      io.writeBackStage.inst(0).info.reg_wen &&
-      io.ctrl.allow_to_go &&
-      !(HasExcInt(io.writeBackStage.inst(0).ex))
+  io.regfile.wen :=
+    io.writeBackStage.data.info.valid &&
+      io.ctrl.ctrlSignal.allow_to_go &&
+      io.writeBackStage.data.info.reg_wen &&
+      !(HasExcInt(io.writeBackStage.data.ex))
 
-  io.regfile(1).wen :=
-    io.writeBackStage.inst(1).info.valid &&
-      io.writeBackStage.inst(1).info.reg_wen &&
-      io.ctrl.allow_to_go &&
-      !(HasExcInt(io.writeBackStage.inst(0).ex)) &&
-      !(HasExcInt(io.writeBackStage.inst(1).ex))
+  io.regfile.waddr := io.writeBackStage.data.info.reg_waddr
+  io.regfile.wdata := io.writeBackStage.data.rd_info.wdata(io.writeBackStage.data.info.fusel)
 
-  for (i <- 0 until (cpuConfig.commitNum)) {
-    io.regfile(i).waddr := io.writeBackStage.inst(i).info.reg_waddr
-    io.regfile(i).wdata := io.writeBackStage.inst(i).rd_info.wdata(io.writeBackStage.inst(i).info.fusel)
-  }
-
-  if (cpuConfig.hasCommitBuffer) {
-    val buffer = Module(new CommitBuffer()).io
-    for (i <- 0 until (cpuConfig.commitNum)) {
-      buffer.enq(i).wb_pc       := io.writeBackStage.inst(i).pc
-      buffer.enq(i).wb_rf_wen   := io.writeBackStage.inst(i).info.valid && io.ctrl.allow_to_go
-      buffer.enq(i).wb_rf_wnum  := io.regfile(i).waddr
-      buffer.enq(i).wb_rf_wdata := io.regfile(i).wdata
-    }
-    buffer.flush         := io.ctrl.do_flush
-    io.debug.wb_pc       := buffer.deq.wb_pc
-    io.debug.wb_rf_wen   := buffer.deq.wb_rf_wen
-    io.debug.wb_rf_wnum  := buffer.deq.wb_rf_wnum
-    io.debug.wb_rf_wdata := buffer.deq.wb_rf_wdata
-  } else {
-    io.debug.wb_pc := Mux(
-      clock.asBool,
-      io.writeBackStage.inst(0).pc,
-      Mux(
-        !(io.writeBackStage.inst(1).info.valid && io.ctrl.allow_to_go),
-        0.U,
-        io.writeBackStage.inst(1).pc
-      )
-    )
-    io.debug.wb_rf_wen := Mux(
-      clock.asBool,
-      io.writeBackStage.inst(0).info.valid && io.ctrl.allow_to_go,
-      io.writeBackStage.inst(1).info.valid && io.ctrl.allow_to_go
-    )
-    io.debug.wb_rf_wnum := Mux(
-      clock.asBool,
-      io.regfile(0).waddr,
-      io.regfile(1).waddr
-    )
-    io.debug.wb_rf_wdata := Mux(
-      clock.asBool,
-      io.regfile(0).wdata,
-      io.regfile(1).wdata
-    )
-  }
+  io.debug.wb_pc       := io.writeBackStage.data.pc
+  io.debug.wb_rf_wen   := io.writeBackStage.data.info.valid && io.ctrl.ctrlSignal.allow_to_go
+  io.debug.wb_rf_wnum  := io.regfile.waddr
+  io.debug.wb_rf_wdata := io.regfile.wdata
 }