重构exe stage级接口
This commit is contained in:
Liphen
parent
2bff20053d
commit
4448b9639b
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@ -1 +1 @@
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Subproject commit 718bf7d977b13729ff0b15a96415f65ac848183e
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Subproject commit bf80bb15c01626d4fe1a6c4085b279d033291279
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@ -10,7 +10,7 @@ import cpu.pipeline.execute.DecodeUnitExecuteUnit
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import cpu.pipeline.fetch.BufferUnit
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import cpu.pipeline.execute
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class InstFifoDecodeUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
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class DecodeUnitInstFifo(implicit val cpuConfig: CpuConfig) extends Bundle {
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val allow_to_go = Output(Vec(cpuConfig.decoderNum, Bool()))
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val inst = Input(Vec(cpuConfig.decoderNum, new BufferUnit()))
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val info = Input(new Bundle {
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@ -40,7 +40,7 @@ class DecoderBranchPredictorUnit extends Bundle {
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class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExceptionNO with HasCSRConst {
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val io = IO(new Bundle {
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// 输入
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val instFifo = new InstFifoDecodeUnit()
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val instFifo = new DecodeUnitInstFifo()
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val regfile = Vec(cpuConfig.decoderNum, new Src12Read())
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val forward = Input(Vec(cpuConfig.commitNum, new DataForwardToDecodeUnit()))
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val csr = Input(new execute.CsrDecodeUnit())
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@ -76,18 +76,16 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep
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issue.decodeInst(i) := info(i)
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issue.execute(i).mem_wreg := io.forward(i).mem_wreg
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issue.execute(i).reg_waddr := io.forward(i).exe.waddr
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io.regfile(i).src1.raddr := info(i).src1_raddr
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io.regfile(i).src2.raddr := info(i).src2_raddr
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}
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io.regfile(0).src1.raddr := info(0).src1_raddr
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io.regfile(0).src2.raddr := info(0).src2_raddr
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io.regfile(1).src1.raddr := info(1).src1_raddr
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io.regfile(1).src2.raddr := info(1).src2_raddr
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forwardCtrl.in.forward := io.forward
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forwardCtrl.in.regfile := io.regfile
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jumpCtrl.in.info := info(0)
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jumpCtrl.in.forward := io.forward
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jumpCtrl.in.pc := pc(0)
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jumpCtrl.in.src_info := io.executeStage.inst0.src_info
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forwardCtrl.in.forward := io.forward
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forwardCtrl.in.regfile := io.regfile
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jumpCtrl.in.info := info(0)
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jumpCtrl.in.forward := io.forward
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jumpCtrl.in.pc := pc(0)
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jumpCtrl.in.src_info := io.executeStage.inst(0).src_info
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val inst0_branch = jumpCtrl.out.jump || io.bpu.branch
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@ -105,88 +103,50 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep
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io.ctrl.inst0.src2.raddr := info(0).src2_raddr
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io.ctrl.branch := io.fetchUnit.branch
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io.executeStage.inst0.pc := pc(0)
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io.executeStage.inst0.info := info(0)
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io.executeStage.inst0.src_info.src1_data := MuxCase(
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SignedExtend(pc(0), XLEN),
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Seq(
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info(0).src1_ren -> forwardCtrl.out.inst(0).src1.rdata,
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(info(0).inst(6, 0) === "b0110111".U) -> 0.U
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io.executeStage.jump_branch_info.jump_regiser := jumpCtrl.out.jump_register
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io.executeStage.jump_branch_info.branch_inst := io.bpu.branch_inst
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io.executeStage.jump_branch_info.pred_branch := io.bpu.branch
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io.executeStage.jump_branch_info.branch_target := io.bpu.target
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io.executeStage.jump_branch_info.update_pht_index := io.bpu.update_pht_index
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for (i <- 0 until (cpuConfig.commitNum)) {
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io.executeStage.inst(i).pc := pc(i)
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io.executeStage.inst(i).info := info(i)
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io.executeStage.inst(i).src_info.src1_data := MuxCase(
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SignedExtend(pc(i), XLEN),
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Seq(
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info(i).src1_ren -> forwardCtrl.out.inst(i).src1.rdata,
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(info(i).inst(6, 0) === "b0110111".U) -> 0.U
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)
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)
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)
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io.executeStage.inst0.src_info.src2_data := Mux(
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info(0).src2_ren,
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forwardCtrl.out.inst(0).src2.rdata,
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info(0).imm
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)
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(0 until (INT_WID)).foreach(i => io.executeStage.inst0.ex.interrupt(i) := io.csr.interrupt(i))
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io.executeStage.inst0.ex.exception.map(_ := false.B)
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io.executeStage.inst0.ex.exception(illegalInstr) := !info(0).inst_legal
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io.executeStage.inst0.ex.exception(instrAccessFault) := io.instFifo.inst(0).access_fault
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io.executeStage.inst0.ex.exception(instrPageFault) := io.instFifo.inst(0).page_fault
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io.executeStage.inst0.ex.exception(instrAddrMisaligned) := pc(0)(log2Ceil(INST_WID / 8) - 1, 0).orR ||
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io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch
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io.executeStage.inst0.ex.exception(breakPoint) := info(0).inst(31, 20) === privEbreak &&
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info(0).op === CSROpType.jmp && info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.exception(ecallM) := info(0).inst(31, 20) === privEcall &&
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info(0).op === CSROpType.jmp && mode === ModeM && info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.exception(ecallS) := info(0).inst(31, 20) === privEcall &&
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info(0).op === CSROpType.jmp && mode === ModeS && info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.exception(ecallU) := info(0).inst(31, 20) === privEcall &&
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info(0).op === CSROpType.jmp && mode === ModeU && info(0).fusel === FuType.csr
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io.executeStage.inst0.ex.tval.map(_ := DontCare)
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io.executeStage.inst0.ex.tval(instrPageFault) := pc(0)
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io.executeStage.inst0.ex.tval(instrAccessFault) := pc(0)
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io.executeStage.inst0.ex.tval(illegalInstr) := info(0).inst
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io.executeStage.inst0.ex.tval(instrAddrMisaligned) := Mux(
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io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch,
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io.fetchUnit.target,
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pc(0)
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)
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io.executeStage.inst0.jb_info.jump_regiser := jumpCtrl.out.jump_register
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io.executeStage.inst0.jb_info.branch_inst := io.bpu.branch_inst
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io.executeStage.inst0.jb_info.pred_branch := io.bpu.branch
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io.executeStage.inst0.jb_info.branch_target := io.bpu.target
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io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index
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io.executeStage.inst1.pc := pc(1)
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io.executeStage.inst1.info := info(1)
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io.executeStage.inst1.src_info.src1_data := MuxCase(
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SignedExtend(pc(1), XLEN),
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Seq(
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info(1).src1_ren -> forwardCtrl.out.inst(1).src1.rdata,
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(info(1).inst(6, 0) === "b0110111".U) -> 0.U
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io.executeStage.inst(i).src_info.src2_data := Mux(
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info(i).src2_ren,
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forwardCtrl.out.inst(i).src2.rdata,
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info(i).imm
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)
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)
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io.executeStage.inst1.src_info.src2_data := Mux(
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info(1).src2_ren,
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forwardCtrl.out.inst(1).src2.rdata,
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info(1).imm
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)
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(0 until (INT_WID)).foreach(i => io.executeStage.inst1.ex.interrupt(i) := io.csr.interrupt(i))
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io.executeStage.inst1.ex.exception.map(_ := false.B)
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io.executeStage.inst1.ex.exception(illegalInstr) := !info(1).inst_legal
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io.executeStage.inst1.ex.exception(instrAccessFault) := io.instFifo.inst(1).access_fault
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io.executeStage.inst1.ex.exception(instrPageFault) := io.instFifo.inst(1).page_fault
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io.executeStage.inst1.ex.exception(instrAddrMisaligned) := pc(1)(log2Ceil(INST_WID / 8) - 1, 0).orR ||
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(0 until (INT_WID)).foreach(j => io.executeStage.inst(i).ex.interrupt(j) := io.csr.interrupt(j))
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io.executeStage.inst(i).ex.exception.map(_ := false.B)
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io.executeStage.inst(i).ex.exception(illegalInstr) := !info(i).inst_legal
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io.executeStage.inst(i).ex.exception(instrAccessFault) := io.instFifo.inst(i).access_fault
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io.executeStage.inst(i).ex.exception(instrPageFault) := io.instFifo.inst(i).page_fault
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io.executeStage.inst(i).ex.exception(instrAddrMisaligned) := pc(i)(log2Ceil(INST_WID / 8) - 1, 0).orR ||
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io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch
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io.executeStage.inst1.ex.exception(breakPoint) := info(1).inst(31, 20) === privEbreak &&
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info(1).op === CSROpType.jmp && info(1).fusel === FuType.csr
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io.executeStage.inst1.ex.exception(ecallM) := info(1).inst(31, 20) === privEcall &&
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info(1).op === CSROpType.jmp && mode === ModeM && info(1).fusel === FuType.csr
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io.executeStage.inst1.ex.exception(ecallS) := info(1).inst(31, 20) === privEcall &&
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info(1).op === CSROpType.jmp && mode === ModeS && info(1).fusel === FuType.csr
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io.executeStage.inst1.ex.exception(ecallU) := info(1).inst(31, 20) === privEcall &&
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info(1).op === CSROpType.jmp && mode === ModeU && info(1).fusel === FuType.csr
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io.executeStage.inst1.ex.tval.map(_ := DontCare)
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io.executeStage.inst1.ex.tval(instrPageFault) := pc(1)
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io.executeStage.inst1.ex.tval(instrAccessFault) := pc(1)
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io.executeStage.inst1.ex.tval(illegalInstr) := info(1).inst
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io.executeStage.inst1.ex.tval(instrAddrMisaligned) := Mux(
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io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch,
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io.fetchUnit.target,
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pc(1)
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)
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io.executeStage.inst(i).ex.exception(breakPoint) := info(i).inst(31, 20) === privEbreak &&
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info(i).op === CSROpType.jmp && info(i).fusel === FuType.csr
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io.executeStage.inst(i).ex.exception(ecallM) := info(i).inst(31, 20) === privEcall &&
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info(i).op === CSROpType.jmp && mode === ModeM && info(i).fusel === FuType.csr
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io.executeStage.inst(i).ex.exception(ecallS) := info(i).inst(31, 20) === privEcall &&
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info(i).op === CSROpType.jmp && mode === ModeS && info(i).fusel === FuType.csr
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io.executeStage.inst(i).ex.exception(ecallU) := info(i).inst(31, 20) === privEcall &&
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info(i).op === CSROpType.jmp && mode === ModeU && info(i).fusel === FuType.csr
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io.executeStage.inst(i).ex.tval.map(_ := DontCare)
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io.executeStage.inst(i).ex.tval(instrPageFault) := pc(i)
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io.executeStage.inst(i).ex.tval(instrAccessFault) := pc(i)
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io.executeStage.inst(i).ex.tval(illegalInstr) := info(i).inst
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io.executeStage.inst(i).ex.tval(instrAddrMisaligned) := Mux(
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io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch,
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io.fetchUnit.target,
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pc(i)
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)
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}
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}
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@ -5,34 +5,26 @@ import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.{BranchPredictorConfig, CpuConfig}
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import cpu.CpuConfig
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class IdExeInst0 extends Bundle {
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val cpuConfig = new BranchPredictorConfig()
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val pc = UInt(XLEN.W)
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val info = new InstInfo()
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val src_info = new SrcInfo()
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val ex = new ExceptionInfo()
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val jb_info = new Bundle {
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// jump ctrl
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val jump_regiser = Bool()
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// bpu
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val branch_inst = Bool()
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val pred_branch = Bool()
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val branch_target = UInt(XLEN.W)
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val update_pht_index = UInt(cpuConfig.phtDepth.W)
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}
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}
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class IdExeInst1 extends Bundle {
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class IdExeInstInfo extends Bundle {
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val pc = UInt(XLEN.W)
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val info = new InstInfo()
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val src_info = new SrcInfo()
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val ex = new ExceptionInfo()
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}
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class DecodeUnitExecuteUnit extends Bundle {
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val inst0 = new IdExeInst0()
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val inst1 = new IdExeInst1()
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class JumpBranchInfo extends Bundle {
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val jump_regiser = Bool()
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val branch_inst = Bool()
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val pred_branch = Bool()
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val branch_target = UInt(XLEN.W)
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val update_pht_index = UInt(XLEN.W)
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}
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class DecodeUnitExecuteUnit(implicit cpuConfig: CpuConfig) extends Bundle {
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val inst = Vec(cpuConfig.commitNum, new IdExeInstInfo())
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val jump_branch_info = new JumpBranchInfo()
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}
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class ExecuteStage(implicit val cpuConfig: CpuConfig) extends Module {
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@ -45,21 +37,24 @@ class ExecuteStage(implicit val cpuConfig: CpuConfig) extends Module {
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val executeUnit = Output(new DecodeUnitExecuteUnit())
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})
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val inst0 = RegInit(0.U.asTypeOf(new IdExeInst0()))
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val inst1 = RegInit(0.U.asTypeOf(new IdExeInst1()))
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val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new IdExeInstInfo())))
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val jump_branch_info = RegInit(0.U.asTypeOf(new JumpBranchInfo()))
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for (i <- 0 until (cpuConfig.commitNum)) {
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when(io.ctrl.clear(i)) {
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inst(i) := 0.U.asTypeOf(new IdExeInstInfo())
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}.elsewhen(io.ctrl.allow_to_go(i)) {
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inst(i) := io.decodeUnit.inst(i)
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}
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}
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// inst0携带分支预测相关信息
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when(io.ctrl.clear(0)) {
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inst0 := 0.U.asTypeOf(new IdExeInst0())
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jump_branch_info := 0.U.asTypeOf(new JumpBranchInfo())
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}.elsewhen(io.ctrl.allow_to_go(0)) {
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inst0 := io.decodeUnit.inst0
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jump_branch_info := io.decodeUnit.jump_branch_info
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}
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when(io.ctrl.clear(1)) {
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inst1 := 0.U.asTypeOf(new IdExeInst1())
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}.elsewhen(io.ctrl.allow_to_go(1)) {
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inst1 := io.decodeUnit.inst1
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}
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io.executeUnit.inst0 := inst0
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io.executeUnit.inst1 := inst1
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io.executeUnit.inst := inst
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io.executeUnit.jump_branch_info := jump_branch_info
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}
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@ -39,88 +39,87 @@ class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module {
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val fu = Module(new Fu()).io
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val valid = VecInit(
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io.executeStage.inst0.info.valid && io.ctrl.allow_to_go,
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io.executeStage.inst1.info.valid && io.ctrl.allow_to_go
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io.executeStage.inst(0).info.valid && io.ctrl.allow_to_go,
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io.executeStage.inst(1).info.valid && io.ctrl.allow_to_go
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)
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val fusel = VecInit(
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io.executeStage.inst0.info.fusel,
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io.executeStage.inst1.info.fusel
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io.executeStage.inst(0).info.fusel,
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io.executeStage.inst(1).info.fusel
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)
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val is_csr = VecInit(
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fusel(0) === FuType.csr && valid(0) &&
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!(HasExcInt(io.executeStage.inst0.ex)),
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!(HasExcInt(io.executeStage.inst(0).ex)),
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fusel(1) === FuType.csr && valid(1) &&
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!(HasExcInt(io.executeStage.inst1.ex))
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!(HasExcInt(io.executeStage.inst(1).ex))
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)
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val mem_wreg = VecInit(
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io.executeStage.inst0.info.fusel === FuType.lsu && io.executeStage.inst0.info.reg_wen,
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io.executeStage.inst1.info.fusel === FuType.lsu && io.executeStage.inst1.info.reg_wen
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io.executeStage.inst(0).info.fusel === FuType.lsu && io.executeStage.inst(0).info.reg_wen,
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io.executeStage.inst(1).info.fusel === FuType.lsu && io.executeStage.inst(1).info.reg_wen
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)
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io.ctrl.inst(0).mem_wreg := mem_wreg(0)
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io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.info.reg_waddr
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io.ctrl.inst(0).reg_waddr := io.executeStage.inst(0).info.reg_waddr
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io.ctrl.inst(1).mem_wreg := mem_wreg(1)
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io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.info.reg_waddr
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io.ctrl.inst(1).reg_waddr := io.executeStage.inst(1).info.reg_waddr
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io.ctrl.flush := io.fetchUnit.flush
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io.csr.in.valid := is_csr.asUInt.orR
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io.csr.in.pc := MuxCase(
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0.U,
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Seq(
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is_csr(0) -> io.executeStage.inst0.pc,
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is_csr(1) -> io.executeStage.inst1.pc
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is_csr(0) -> io.executeStage.inst(0).pc,
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is_csr(1) -> io.executeStage.inst(1).pc
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)
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)
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io.csr.in.info := MuxCase(
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0.U.asTypeOf(new InstInfo()),
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Seq(
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is_csr(0) -> io.executeStage.inst0.info,
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is_csr(1) -> io.executeStage.inst1.info
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is_csr(0) -> io.executeStage.inst(0).info,
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is_csr(1) -> io.executeStage.inst(1).info
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)
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)
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io.csr.in.src_info := MuxCase(
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0.U.asTypeOf(new SrcInfo()),
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Seq(
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is_csr(0) -> io.executeStage.inst0.src_info,
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is_csr(1) -> io.executeStage.inst1.src_info
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is_csr(0) -> io.executeStage.inst(0).src_info,
|
||||
is_csr(1) -> io.executeStage.inst(1).src_info
|
||||
)
|
||||
)
|
||||
io.csr.in.ex := MuxCase(
|
||||
0.U.asTypeOf(new ExceptionInfo()),
|
||||
Seq(
|
||||
is_csr(0) -> io.executeStage.inst0.ex,
|
||||
is_csr(1) -> io.executeStage.inst1.ex
|
||||
is_csr(0) -> io.executeStage.inst(0).ex,
|
||||
is_csr(1) -> io.executeStage.inst(1).ex
|
||||
)
|
||||
)
|
||||
|
||||
val is_lsu = VecInit(
|
||||
fusel(0) === FuType.lsu && valid(0) &&
|
||||
!(HasExcInt(io.executeStage.inst0.ex)),
|
||||
!(HasExcInt(io.executeStage.inst(0).ex)),
|
||||
fusel(1) === FuType.lsu && valid(1) &&
|
||||
!(HasExcInt(io.executeStage.inst1.ex))
|
||||
!(HasExcInt(io.executeStage.inst(1).ex))
|
||||
)
|
||||
|
||||
// input fu
|
||||
fu.ctrl <> io.ctrl.fu
|
||||
fu.inst(0).pc := io.executeStage.inst0.pc
|
||||
fu.inst(0).info := io.executeStage.inst0.info
|
||||
fu.inst(0).src_info := io.executeStage.inst0.src_info
|
||||
fu.inst(1).pc := io.executeStage.inst1.pc
|
||||
fu.inst(1).info := io.executeStage.inst1.info
|
||||
fu.inst(1).src_info := io.executeStage.inst1.src_info
|
||||
fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch
|
||||
fu.branch.jump_regiser := io.executeStage.inst0.jb_info.jump_regiser
|
||||
fu.branch.branch_target := io.executeStage.inst0.jb_info.branch_target
|
||||
for (i <- 0 until (cpuConfig.commitNum)) {
|
||||
fu.inst(i).pc := io.executeStage.inst(i).pc
|
||||
fu.inst(i).info := io.executeStage.inst(i).info
|
||||
fu.inst(i).src_info := io.executeStage.inst(i).src_info
|
||||
}
|
||||
fu.branch.pred_branch := io.executeStage.jump_branch_info.pred_branch
|
||||
fu.branch.jump_regiser := io.executeStage.jump_branch_info.jump_regiser
|
||||
fu.branch.branch_target := io.executeStage.jump_branch_info.branch_target
|
||||
|
||||
io.dataMemory.addr := fu.dataMemory.addr
|
||||
|
||||
io.bpu.pc := io.executeStage.inst0.pc
|
||||
io.bpu.update_pht_index := io.executeStage.inst0.jb_info.update_pht_index
|
||||
io.bpu.pc := io.executeStage.inst(0).pc
|
||||
io.bpu.update_pht_index := io.executeStage.jump_branch_info.update_pht_index
|
||||
io.bpu.branch := fu.branch.branch
|
||||
io.bpu.branch_inst := io.executeStage.inst0.jb_info.branch_inst
|
||||
io.bpu.branch_inst := io.executeStage.jump_branch_info.branch_inst
|
||||
|
||||
io.fetchUnit.flush := valid(0) && io.ctrl.allow_to_go &&
|
||||
(fu.branch.flush || io.csr.out.flush)
|
||||
|
|
@ -128,56 +127,56 @@ class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module {
|
|||
|
||||
io.ctrl.fu_stall := fu.stall_req
|
||||
|
||||
io.memoryStage.inst0.pc := io.executeStage.inst0.pc
|
||||
io.memoryStage.inst0.info := io.executeStage.inst0.info
|
||||
io.memoryStage.inst0.src_info := io.executeStage.inst0.src_info
|
||||
io.memoryStage.inst0.pc := io.executeStage.inst(0).pc
|
||||
io.memoryStage.inst0.info := io.executeStage.inst(0).info
|
||||
io.memoryStage.inst0.src_info := io.executeStage.inst(0).src_info
|
||||
io.memoryStage.inst0.rd_info.wdata := DontCare
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.alu) := fu.inst(0).result.alu
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.bru) := io.executeStage.inst0.pc + 4.U
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.bru) := io.executeStage.inst(0).pc + 4.U
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.mdu) := fu.inst(0).result.mdu
|
||||
io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata
|
||||
val has_ex0 =
|
||||
(HasExcInt(io.executeStage.inst0.ex)) && io.executeStage.inst0.info.valid
|
||||
(HasExcInt(io.executeStage.inst(0).ex)) && io.executeStage.inst(0).info.valid
|
||||
io.memoryStage.inst0.ex := Mux(
|
||||
has_ex0,
|
||||
io.executeStage.inst0.ex,
|
||||
MuxLookup(io.executeStage.inst0.info.fusel, io.executeStage.inst0.ex)(
|
||||
io.executeStage.inst(0).ex,
|
||||
MuxLookup(io.executeStage.inst(0).info.fusel, io.executeStage.inst(0).ex)(
|
||||
Seq(
|
||||
FuType.csr -> io.csr.out.ex
|
||||
)
|
||||
)
|
||||
)
|
||||
io.memoryStage.inst0.ex.exception(instrAddrMisaligned) := io.executeStage.inst0.ex.exception(instrAddrMisaligned) ||
|
||||
io.memoryStage.inst0.ex.exception(instrAddrMisaligned) := io.executeStage.inst(0).ex.exception(instrAddrMisaligned) ||
|
||||
io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR
|
||||
io.memoryStage.inst0.ex.tval(instrAddrMisaligned) := Mux(
|
||||
io.executeStage.inst0.ex.exception(instrAddrMisaligned),
|
||||
io.executeStage.inst0.ex.tval(instrAddrMisaligned),
|
||||
io.executeStage.inst(0).ex.exception(instrAddrMisaligned),
|
||||
io.executeStage.inst(0).ex.tval(instrAddrMisaligned),
|
||||
io.fetchUnit.target
|
||||
)
|
||||
|
||||
io.memoryStage.inst1.pc := io.executeStage.inst1.pc
|
||||
io.memoryStage.inst1.info := io.executeStage.inst1.info
|
||||
io.memoryStage.inst1.src_info := io.executeStage.inst1.src_info
|
||||
io.memoryStage.inst1.pc := io.executeStage.inst(1).pc
|
||||
io.memoryStage.inst1.info := io.executeStage.inst(1).info
|
||||
io.memoryStage.inst1.src_info := io.executeStage.inst(1).src_info
|
||||
io.memoryStage.inst1.rd_info.wdata := DontCare
|
||||
io.memoryStage.inst1.rd_info.wdata(FuType.alu) := fu.inst(1).result.alu
|
||||
io.memoryStage.inst1.rd_info.wdata(FuType.mdu) := fu.inst(1).result.mdu
|
||||
io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata
|
||||
val has_ex1 =
|
||||
(HasExcInt(io.executeStage.inst1.ex)) && io.executeStage.inst1.info.valid
|
||||
(HasExcInt(io.executeStage.inst(1).ex)) && io.executeStage.inst(1).info.valid
|
||||
io.memoryStage.inst1.ex := Mux(
|
||||
has_ex1,
|
||||
io.executeStage.inst1.ex,
|
||||
MuxLookup(io.executeStage.inst1.info.fusel, io.executeStage.inst1.ex)(
|
||||
io.executeStage.inst(1).ex,
|
||||
MuxLookup(io.executeStage.inst(1).info.fusel, io.executeStage.inst(1).ex)(
|
||||
Seq(
|
||||
FuType.csr -> io.csr.out.ex
|
||||
)
|
||||
)
|
||||
)
|
||||
io.memoryStage.inst1.ex.exception(instrAddrMisaligned) := io.executeStage.inst1.ex.exception(instrAddrMisaligned) ||
|
||||
io.memoryStage.inst1.ex.exception(instrAddrMisaligned) := io.executeStage.inst(1).ex.exception(instrAddrMisaligned) ||
|
||||
io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR
|
||||
io.memoryStage.inst1.ex.tval(instrAddrMisaligned) := Mux(
|
||||
io.executeStage.inst1.ex.exception(instrAddrMisaligned),
|
||||
io.executeStage.inst1.ex.tval(instrAddrMisaligned),
|
||||
io.executeStage.inst(1).ex.exception(instrAddrMisaligned),
|
||||
io.executeStage.inst(1).ex.tval(instrAddrMisaligned),
|
||||
io.fetchUnit.target
|
||||
)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue