diff --git a/chisel/difftest b/chisel/difftest index 718bf7d..bf80bb1 160000 --- a/chisel/difftest +++ b/chisel/difftest @@ -1 +1 @@ -Subproject commit 718bf7d977b13729ff0b15a96415f65ac848183e +Subproject commit bf80bb15c01626d4fe1a6c4085b279d033291279 diff --git a/chisel/playground/src/pipeline/decode/DecodeUnit.scala b/chisel/playground/src/pipeline/decode/DecodeUnit.scala index 8cfd1ca..fb08559 100644 --- a/chisel/playground/src/pipeline/decode/DecodeUnit.scala +++ b/chisel/playground/src/pipeline/decode/DecodeUnit.scala @@ -10,7 +10,7 @@ import cpu.pipeline.execute.DecodeUnitExecuteUnit import cpu.pipeline.fetch.BufferUnit import cpu.pipeline.execute -class InstFifoDecodeUnit(implicit val cpuConfig: CpuConfig) extends Bundle { +class DecodeUnitInstFifo(implicit val cpuConfig: CpuConfig) extends Bundle { val allow_to_go = Output(Vec(cpuConfig.decoderNum, Bool())) val inst = Input(Vec(cpuConfig.decoderNum, new BufferUnit())) val info = Input(new Bundle { @@ -40,7 +40,7 @@ class DecoderBranchPredictorUnit extends Bundle { class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExceptionNO with HasCSRConst { val io = IO(new Bundle { // 输入 - val instFifo = new InstFifoDecodeUnit() + val instFifo = new DecodeUnitInstFifo() val regfile = Vec(cpuConfig.decoderNum, new Src12Read()) val forward = Input(Vec(cpuConfig.commitNum, new DataForwardToDecodeUnit())) val csr = Input(new execute.CsrDecodeUnit()) @@ -76,18 +76,16 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep issue.decodeInst(i) := info(i) issue.execute(i).mem_wreg := io.forward(i).mem_wreg issue.execute(i).reg_waddr := io.forward(i).exe.waddr + io.regfile(i).src1.raddr := info(i).src1_raddr + io.regfile(i).src2.raddr := info(i).src2_raddr } - io.regfile(0).src1.raddr := info(0).src1_raddr - io.regfile(0).src2.raddr := info(0).src2_raddr - io.regfile(1).src1.raddr := info(1).src1_raddr - io.regfile(1).src2.raddr := info(1).src2_raddr - forwardCtrl.in.forward := io.forward - forwardCtrl.in.regfile := io.regfile - jumpCtrl.in.info := info(0) - jumpCtrl.in.forward := io.forward - jumpCtrl.in.pc := pc(0) - jumpCtrl.in.src_info := io.executeStage.inst0.src_info + forwardCtrl.in.forward := io.forward + forwardCtrl.in.regfile := io.regfile + jumpCtrl.in.info := info(0) + jumpCtrl.in.forward := io.forward + jumpCtrl.in.pc := pc(0) + jumpCtrl.in.src_info := io.executeStage.inst(0).src_info val inst0_branch = jumpCtrl.out.jump || io.bpu.branch @@ -105,88 +103,50 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep io.ctrl.inst0.src2.raddr := info(0).src2_raddr io.ctrl.branch := io.fetchUnit.branch - io.executeStage.inst0.pc := pc(0) - io.executeStage.inst0.info := info(0) - io.executeStage.inst0.src_info.src1_data := MuxCase( - SignedExtend(pc(0), XLEN), - Seq( - info(0).src1_ren -> forwardCtrl.out.inst(0).src1.rdata, - (info(0).inst(6, 0) === "b0110111".U) -> 0.U + io.executeStage.jump_branch_info.jump_regiser := jumpCtrl.out.jump_register + io.executeStage.jump_branch_info.branch_inst := io.bpu.branch_inst + io.executeStage.jump_branch_info.pred_branch := io.bpu.branch + io.executeStage.jump_branch_info.branch_target := io.bpu.target + io.executeStage.jump_branch_info.update_pht_index := io.bpu.update_pht_index + + for (i <- 0 until (cpuConfig.commitNum)) { + io.executeStage.inst(i).pc := pc(i) + io.executeStage.inst(i).info := info(i) + io.executeStage.inst(i).src_info.src1_data := MuxCase( + SignedExtend(pc(i), XLEN), + Seq( + info(i).src1_ren -> forwardCtrl.out.inst(i).src1.rdata, + (info(i).inst(6, 0) === "b0110111".U) -> 0.U + ) ) - ) - io.executeStage.inst0.src_info.src2_data := Mux( - info(0).src2_ren, - forwardCtrl.out.inst(0).src2.rdata, - info(0).imm - ) - (0 until (INT_WID)).foreach(i => io.executeStage.inst0.ex.interrupt(i) := io.csr.interrupt(i)) - io.executeStage.inst0.ex.exception.map(_ := false.B) - io.executeStage.inst0.ex.exception(illegalInstr) := !info(0).inst_legal - io.executeStage.inst0.ex.exception(instrAccessFault) := io.instFifo.inst(0).access_fault - io.executeStage.inst0.ex.exception(instrPageFault) := io.instFifo.inst(0).page_fault - io.executeStage.inst0.ex.exception(instrAddrMisaligned) := pc(0)(log2Ceil(INST_WID / 8) - 1, 0).orR || - io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch - io.executeStage.inst0.ex.exception(breakPoint) := info(0).inst(31, 20) === privEbreak && - info(0).op === CSROpType.jmp && info(0).fusel === FuType.csr - io.executeStage.inst0.ex.exception(ecallM) := info(0).inst(31, 20) === privEcall && - info(0).op === CSROpType.jmp && mode === ModeM && info(0).fusel === FuType.csr - io.executeStage.inst0.ex.exception(ecallS) := info(0).inst(31, 20) === privEcall && - info(0).op === CSROpType.jmp && mode === ModeS && info(0).fusel === FuType.csr - io.executeStage.inst0.ex.exception(ecallU) := info(0).inst(31, 20) === privEcall && - info(0).op === CSROpType.jmp && mode === ModeU && info(0).fusel === FuType.csr - io.executeStage.inst0.ex.tval.map(_ := DontCare) - io.executeStage.inst0.ex.tval(instrPageFault) := pc(0) - io.executeStage.inst0.ex.tval(instrAccessFault) := pc(0) - io.executeStage.inst0.ex.tval(illegalInstr) := info(0).inst - io.executeStage.inst0.ex.tval(instrAddrMisaligned) := Mux( - io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch, - io.fetchUnit.target, - pc(0) - ) - - io.executeStage.inst0.jb_info.jump_regiser := jumpCtrl.out.jump_register - io.executeStage.inst0.jb_info.branch_inst := io.bpu.branch_inst - io.executeStage.inst0.jb_info.pred_branch := io.bpu.branch - io.executeStage.inst0.jb_info.branch_target := io.bpu.target - io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index - - io.executeStage.inst1.pc := pc(1) - io.executeStage.inst1.info := info(1) - io.executeStage.inst1.src_info.src1_data := MuxCase( - SignedExtend(pc(1), XLEN), - Seq( - info(1).src1_ren -> forwardCtrl.out.inst(1).src1.rdata, - (info(1).inst(6, 0) === "b0110111".U) -> 0.U + io.executeStage.inst(i).src_info.src2_data := Mux( + info(i).src2_ren, + forwardCtrl.out.inst(i).src2.rdata, + info(i).imm ) - ) - io.executeStage.inst1.src_info.src2_data := Mux( - info(1).src2_ren, - forwardCtrl.out.inst(1).src2.rdata, - info(1).imm - ) - (0 until (INT_WID)).foreach(i => io.executeStage.inst1.ex.interrupt(i) := io.csr.interrupt(i)) - io.executeStage.inst1.ex.exception.map(_ := false.B) - io.executeStage.inst1.ex.exception(illegalInstr) := !info(1).inst_legal - io.executeStage.inst1.ex.exception(instrAccessFault) := io.instFifo.inst(1).access_fault - io.executeStage.inst1.ex.exception(instrPageFault) := io.instFifo.inst(1).page_fault - io.executeStage.inst1.ex.exception(instrAddrMisaligned) := pc(1)(log2Ceil(INST_WID / 8) - 1, 0).orR || + (0 until (INT_WID)).foreach(j => io.executeStage.inst(i).ex.interrupt(j) := io.csr.interrupt(j)) + io.executeStage.inst(i).ex.exception.map(_ := false.B) + io.executeStage.inst(i).ex.exception(illegalInstr) := !info(i).inst_legal + io.executeStage.inst(i).ex.exception(instrAccessFault) := io.instFifo.inst(i).access_fault + io.executeStage.inst(i).ex.exception(instrPageFault) := io.instFifo.inst(i).page_fault + io.executeStage.inst(i).ex.exception(instrAddrMisaligned) := pc(i)(log2Ceil(INST_WID / 8) - 1, 0).orR || io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch - io.executeStage.inst1.ex.exception(breakPoint) := info(1).inst(31, 20) === privEbreak && - info(1).op === CSROpType.jmp && info(1).fusel === FuType.csr - io.executeStage.inst1.ex.exception(ecallM) := info(1).inst(31, 20) === privEcall && - info(1).op === CSROpType.jmp && mode === ModeM && info(1).fusel === FuType.csr - io.executeStage.inst1.ex.exception(ecallS) := info(1).inst(31, 20) === privEcall && - info(1).op === CSROpType.jmp && mode === ModeS && info(1).fusel === FuType.csr - io.executeStage.inst1.ex.exception(ecallU) := info(1).inst(31, 20) === privEcall && - info(1).op === CSROpType.jmp && mode === ModeU && info(1).fusel === FuType.csr - io.executeStage.inst1.ex.tval.map(_ := DontCare) - io.executeStage.inst1.ex.tval(instrPageFault) := pc(1) - io.executeStage.inst1.ex.tval(instrAccessFault) := pc(1) - io.executeStage.inst1.ex.tval(illegalInstr) := info(1).inst - io.executeStage.inst1.ex.tval(instrAddrMisaligned) := Mux( - io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch, - io.fetchUnit.target, - pc(1) - ) - + io.executeStage.inst(i).ex.exception(breakPoint) := info(i).inst(31, 20) === privEbreak && + info(i).op === CSROpType.jmp && info(i).fusel === FuType.csr + io.executeStage.inst(i).ex.exception(ecallM) := info(i).inst(31, 20) === privEcall && + info(i).op === CSROpType.jmp && mode === ModeM && info(i).fusel === FuType.csr + io.executeStage.inst(i).ex.exception(ecallS) := info(i).inst(31, 20) === privEcall && + info(i).op === CSROpType.jmp && mode === ModeS && info(i).fusel === FuType.csr + io.executeStage.inst(i).ex.exception(ecallU) := info(i).inst(31, 20) === privEcall && + info(i).op === CSROpType.jmp && mode === ModeU && info(i).fusel === FuType.csr + io.executeStage.inst(i).ex.tval.map(_ := DontCare) + io.executeStage.inst(i).ex.tval(instrPageFault) := pc(i) + io.executeStage.inst(i).ex.tval(instrAccessFault) := pc(i) + io.executeStage.inst(i).ex.tval(illegalInstr) := info(i).inst + io.executeStage.inst(i).ex.tval(instrAddrMisaligned) := Mux( + io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR && io.fetchUnit.branch, + io.fetchUnit.target, + pc(i) + ) + } } diff --git a/chisel/playground/src/pipeline/execute/ExecuteStage.scala b/chisel/playground/src/pipeline/execute/ExecuteStage.scala index 9b948a6..bcbb8f0 100644 --- a/chisel/playground/src/pipeline/execute/ExecuteStage.scala +++ b/chisel/playground/src/pipeline/execute/ExecuteStage.scala @@ -5,34 +5,26 @@ import chisel3.util._ import cpu.defines._ import cpu.defines.Const._ import cpu.{BranchPredictorConfig, CpuConfig} +import cpu.CpuConfig -class IdExeInst0 extends Bundle { - val cpuConfig = new BranchPredictorConfig() - val pc = UInt(XLEN.W) - val info = new InstInfo() - val src_info = new SrcInfo() - val ex = new ExceptionInfo() - val jb_info = new Bundle { - // jump ctrl - val jump_regiser = Bool() - // bpu - val branch_inst = Bool() - val pred_branch = Bool() - val branch_target = UInt(XLEN.W) - val update_pht_index = UInt(cpuConfig.phtDepth.W) - } -} - -class IdExeInst1 extends Bundle { +class IdExeInstInfo extends Bundle { val pc = UInt(XLEN.W) val info = new InstInfo() val src_info = new SrcInfo() val ex = new ExceptionInfo() } -class DecodeUnitExecuteUnit extends Bundle { - val inst0 = new IdExeInst0() - val inst1 = new IdExeInst1() +class JumpBranchInfo extends Bundle { + val jump_regiser = Bool() + val branch_inst = Bool() + val pred_branch = Bool() + val branch_target = UInt(XLEN.W) + val update_pht_index = UInt(XLEN.W) +} + +class DecodeUnitExecuteUnit(implicit cpuConfig: CpuConfig) extends Bundle { + val inst = Vec(cpuConfig.commitNum, new IdExeInstInfo()) + val jump_branch_info = new JumpBranchInfo() } class ExecuteStage(implicit val cpuConfig: CpuConfig) extends Module { @@ -45,21 +37,24 @@ class ExecuteStage(implicit val cpuConfig: CpuConfig) extends Module { val executeUnit = Output(new DecodeUnitExecuteUnit()) }) - val inst0 = RegInit(0.U.asTypeOf(new IdExeInst0())) - val inst1 = RegInit(0.U.asTypeOf(new IdExeInst1())) + val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new IdExeInstInfo()))) + val jump_branch_info = RegInit(0.U.asTypeOf(new JumpBranchInfo())) + for (i <- 0 until (cpuConfig.commitNum)) { + when(io.ctrl.clear(i)) { + inst(i) := 0.U.asTypeOf(new IdExeInstInfo()) + }.elsewhen(io.ctrl.allow_to_go(i)) { + inst(i) := io.decodeUnit.inst(i) + } + } + + // inst0携带分支预测相关信息 when(io.ctrl.clear(0)) { - inst0 := 0.U.asTypeOf(new IdExeInst0()) + jump_branch_info := 0.U.asTypeOf(new JumpBranchInfo()) }.elsewhen(io.ctrl.allow_to_go(0)) { - inst0 := io.decodeUnit.inst0 + jump_branch_info := io.decodeUnit.jump_branch_info } - when(io.ctrl.clear(1)) { - inst1 := 0.U.asTypeOf(new IdExeInst1()) - }.elsewhen(io.ctrl.allow_to_go(1)) { - inst1 := io.decodeUnit.inst1 - } - - io.executeUnit.inst0 := inst0 - io.executeUnit.inst1 := inst1 + io.executeUnit.inst := inst + io.executeUnit.jump_branch_info := jump_branch_info } diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala index ec32f1f..10eb415 100644 --- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala +++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala @@ -39,88 +39,87 @@ class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module { val fu = Module(new Fu()).io val valid = VecInit( - io.executeStage.inst0.info.valid && io.ctrl.allow_to_go, - io.executeStage.inst1.info.valid && io.ctrl.allow_to_go + io.executeStage.inst(0).info.valid && io.ctrl.allow_to_go, + io.executeStage.inst(1).info.valid && io.ctrl.allow_to_go ) val fusel = VecInit( - io.executeStage.inst0.info.fusel, - io.executeStage.inst1.info.fusel + io.executeStage.inst(0).info.fusel, + io.executeStage.inst(1).info.fusel ) val is_csr = VecInit( fusel(0) === FuType.csr && valid(0) && - !(HasExcInt(io.executeStage.inst0.ex)), + !(HasExcInt(io.executeStage.inst(0).ex)), fusel(1) === FuType.csr && valid(1) && - !(HasExcInt(io.executeStage.inst1.ex)) + !(HasExcInt(io.executeStage.inst(1).ex)) ) val mem_wreg = VecInit( - io.executeStage.inst0.info.fusel === FuType.lsu && io.executeStage.inst0.info.reg_wen, - io.executeStage.inst1.info.fusel === FuType.lsu && io.executeStage.inst1.info.reg_wen + io.executeStage.inst(0).info.fusel === FuType.lsu && io.executeStage.inst(0).info.reg_wen, + io.executeStage.inst(1).info.fusel === FuType.lsu && io.executeStage.inst(1).info.reg_wen ) io.ctrl.inst(0).mem_wreg := mem_wreg(0) - io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.info.reg_waddr + io.ctrl.inst(0).reg_waddr := io.executeStage.inst(0).info.reg_waddr io.ctrl.inst(1).mem_wreg := mem_wreg(1) - io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.info.reg_waddr + io.ctrl.inst(1).reg_waddr := io.executeStage.inst(1).info.reg_waddr io.ctrl.flush := io.fetchUnit.flush io.csr.in.valid := is_csr.asUInt.orR io.csr.in.pc := MuxCase( 0.U, Seq( - is_csr(0) -> io.executeStage.inst0.pc, - is_csr(1) -> io.executeStage.inst1.pc + is_csr(0) -> io.executeStage.inst(0).pc, + is_csr(1) -> io.executeStage.inst(1).pc ) ) io.csr.in.info := MuxCase( 0.U.asTypeOf(new InstInfo()), Seq( - is_csr(0) -> io.executeStage.inst0.info, - is_csr(1) -> io.executeStage.inst1.info + is_csr(0) -> io.executeStage.inst(0).info, + is_csr(1) -> io.executeStage.inst(1).info ) ) io.csr.in.src_info := MuxCase( 0.U.asTypeOf(new SrcInfo()), Seq( - is_csr(0) -> io.executeStage.inst0.src_info, - is_csr(1) -> io.executeStage.inst1.src_info + is_csr(0) -> io.executeStage.inst(0).src_info, + is_csr(1) -> io.executeStage.inst(1).src_info ) ) io.csr.in.ex := MuxCase( 0.U.asTypeOf(new ExceptionInfo()), Seq( - is_csr(0) -> io.executeStage.inst0.ex, - is_csr(1) -> io.executeStage.inst1.ex + is_csr(0) -> io.executeStage.inst(0).ex, + is_csr(1) -> io.executeStage.inst(1).ex ) ) val is_lsu = VecInit( fusel(0) === FuType.lsu && valid(0) && - !(HasExcInt(io.executeStage.inst0.ex)), + !(HasExcInt(io.executeStage.inst(0).ex)), fusel(1) === FuType.lsu && valid(1) && - !(HasExcInt(io.executeStage.inst1.ex)) + !(HasExcInt(io.executeStage.inst(1).ex)) ) // input fu fu.ctrl <> io.ctrl.fu - fu.inst(0).pc := io.executeStage.inst0.pc - fu.inst(0).info := io.executeStage.inst0.info - fu.inst(0).src_info := io.executeStage.inst0.src_info - fu.inst(1).pc := io.executeStage.inst1.pc - fu.inst(1).info := io.executeStage.inst1.info - fu.inst(1).src_info := io.executeStage.inst1.src_info - fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch - fu.branch.jump_regiser := io.executeStage.inst0.jb_info.jump_regiser - fu.branch.branch_target := io.executeStage.inst0.jb_info.branch_target + for (i <- 0 until (cpuConfig.commitNum)) { + fu.inst(i).pc := io.executeStage.inst(i).pc + fu.inst(i).info := io.executeStage.inst(i).info + fu.inst(i).src_info := io.executeStage.inst(i).src_info + } + fu.branch.pred_branch := io.executeStage.jump_branch_info.pred_branch + fu.branch.jump_regiser := io.executeStage.jump_branch_info.jump_regiser + fu.branch.branch_target := io.executeStage.jump_branch_info.branch_target io.dataMemory.addr := fu.dataMemory.addr - io.bpu.pc := io.executeStage.inst0.pc - io.bpu.update_pht_index := io.executeStage.inst0.jb_info.update_pht_index + io.bpu.pc := io.executeStage.inst(0).pc + io.bpu.update_pht_index := io.executeStage.jump_branch_info.update_pht_index io.bpu.branch := fu.branch.branch - io.bpu.branch_inst := io.executeStage.inst0.jb_info.branch_inst + io.bpu.branch_inst := io.executeStage.jump_branch_info.branch_inst io.fetchUnit.flush := valid(0) && io.ctrl.allow_to_go && (fu.branch.flush || io.csr.out.flush) @@ -128,56 +127,56 @@ class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module { io.ctrl.fu_stall := fu.stall_req - io.memoryStage.inst0.pc := io.executeStage.inst0.pc - io.memoryStage.inst0.info := io.executeStage.inst0.info - io.memoryStage.inst0.src_info := io.executeStage.inst0.src_info + io.memoryStage.inst0.pc := io.executeStage.inst(0).pc + io.memoryStage.inst0.info := io.executeStage.inst(0).info + io.memoryStage.inst0.src_info := io.executeStage.inst(0).src_info io.memoryStage.inst0.rd_info.wdata := DontCare io.memoryStage.inst0.rd_info.wdata(FuType.alu) := fu.inst(0).result.alu - io.memoryStage.inst0.rd_info.wdata(FuType.bru) := io.executeStage.inst0.pc + 4.U + io.memoryStage.inst0.rd_info.wdata(FuType.bru) := io.executeStage.inst(0).pc + 4.U io.memoryStage.inst0.rd_info.wdata(FuType.mdu) := fu.inst(0).result.mdu io.memoryStage.inst0.rd_info.wdata(FuType.csr) := io.csr.out.rdata val has_ex0 = - (HasExcInt(io.executeStage.inst0.ex)) && io.executeStage.inst0.info.valid + (HasExcInt(io.executeStage.inst(0).ex)) && io.executeStage.inst(0).info.valid io.memoryStage.inst0.ex := Mux( has_ex0, - io.executeStage.inst0.ex, - MuxLookup(io.executeStage.inst0.info.fusel, io.executeStage.inst0.ex)( + io.executeStage.inst(0).ex, + MuxLookup(io.executeStage.inst(0).info.fusel, io.executeStage.inst(0).ex)( Seq( FuType.csr -> io.csr.out.ex ) ) ) - io.memoryStage.inst0.ex.exception(instrAddrMisaligned) := io.executeStage.inst0.ex.exception(instrAddrMisaligned) || + io.memoryStage.inst0.ex.exception(instrAddrMisaligned) := io.executeStage.inst(0).ex.exception(instrAddrMisaligned) || io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR io.memoryStage.inst0.ex.tval(instrAddrMisaligned) := Mux( - io.executeStage.inst0.ex.exception(instrAddrMisaligned), - io.executeStage.inst0.ex.tval(instrAddrMisaligned), + io.executeStage.inst(0).ex.exception(instrAddrMisaligned), + io.executeStage.inst(0).ex.tval(instrAddrMisaligned), io.fetchUnit.target ) - io.memoryStage.inst1.pc := io.executeStage.inst1.pc - io.memoryStage.inst1.info := io.executeStage.inst1.info - io.memoryStage.inst1.src_info := io.executeStage.inst1.src_info + io.memoryStage.inst1.pc := io.executeStage.inst(1).pc + io.memoryStage.inst1.info := io.executeStage.inst(1).info + io.memoryStage.inst1.src_info := io.executeStage.inst(1).src_info io.memoryStage.inst1.rd_info.wdata := DontCare io.memoryStage.inst1.rd_info.wdata(FuType.alu) := fu.inst(1).result.alu io.memoryStage.inst1.rd_info.wdata(FuType.mdu) := fu.inst(1).result.mdu io.memoryStage.inst1.rd_info.wdata(FuType.csr) := io.csr.out.rdata val has_ex1 = - (HasExcInt(io.executeStage.inst1.ex)) && io.executeStage.inst1.info.valid + (HasExcInt(io.executeStage.inst(1).ex)) && io.executeStage.inst(1).info.valid io.memoryStage.inst1.ex := Mux( has_ex1, - io.executeStage.inst1.ex, - MuxLookup(io.executeStage.inst1.info.fusel, io.executeStage.inst1.ex)( + io.executeStage.inst(1).ex, + MuxLookup(io.executeStage.inst(1).info.fusel, io.executeStage.inst(1).ex)( Seq( FuType.csr -> io.csr.out.ex ) ) ) - io.memoryStage.inst1.ex.exception(instrAddrMisaligned) := io.executeStage.inst1.ex.exception(instrAddrMisaligned) || + io.memoryStage.inst1.ex.exception(instrAddrMisaligned) := io.executeStage.inst(1).ex.exception(instrAddrMisaligned) || io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR io.memoryStage.inst1.ex.tval(instrAddrMisaligned) := Mux( - io.executeStage.inst1.ex.exception(instrAddrMisaligned), - io.executeStage.inst1.ex.tval(instrAddrMisaligned), + io.executeStage.inst(1).ex.exception(instrAddrMisaligned), + io.executeStage.inst(1).ex.tval(instrAddrMisaligned), io.fetchUnit.target )