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修改mdu的start为en

This commit is contained in:
Liphen 2024-01-27 16:16:03 +08:00
parent 742d9ba87f
commit 22b417a99e
3 changed files with 17 additions and 17 deletions
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16
chisel/playground/src/pipeline/execute/fu/Div.scala
View File

@ -45,7 +45,7 @@ class Div(implicit cpuConfig: CpuConfig) extends Module {
val src1 = Input(UInt(XLEN.W))
val src2 = Input(UInt(XLEN.W))
val signed = Input(Bool())
val start = Input(Bool())
val en = Input(Bool())
val allow_to_go = Input(Bool())
val ready = Output(Bool())
@ -100,11 +100,11 @@ class Div(implicit cpuConfig: CpuConfig) extends Module {
unsignedDiv_done := false.B
}
// 被除数和除数的valid信号
signedDiv.s_axis_dividend_tvalid := io.start && !signedDiv_sent(0) && io.signed
signedDiv.s_axis_divisor_tvalid := io.start && !signedDiv_sent(1) && io.signed
signedDiv.s_axis_dividend_tvalid := io.en && !signedDiv_sent(0) && io.signed
signedDiv.s_axis_divisor_tvalid := io.en && !signedDiv_sent(1) && io.signed
unsignedDiv.s_axis_dividend_tvalid := io.start && !unsignedDiv_sent(0) && !io.signed
unsignedDiv.s_axis_divisor_tvalid := io.start && !unsignedDiv_sent(1) && !io.signed
unsignedDiv.s_axis_dividend_tvalid := io.en && !unsignedDiv_sent(0) && !io.signed
unsignedDiv.s_axis_divisor_tvalid := io.en && !unsignedDiv_sent(1) && !io.signed
// 被除数和除数的值
signedDiv.s_axis_dividend_tdata := io.src1
@ -128,8 +128,8 @@ class Div(implicit cpuConfig: CpuConfig) extends Module {
cnt := MuxCase(
cnt,
Seq(
(io.start && !io.ready) -> (cnt + 1.U),
io.allow_to_go -> 0.U
(io.en && !io.ready) -> (cnt + 1.U),
io.allow_to_go -> 0.U
)
)
@ -150,7 +150,7 @@ class Div(implicit cpuConfig: CpuConfig) extends Module {
val quotient = RegInit(0.S(XLEN.W))
val remainder = RegInit(0.S(XLEN.W))
when(io.start) {
when(io.en) {
quotient := Mux(quotient_signed, (-quotient_abs).asSInt, quotient_abs.asSInt)
remainder := Mux(remainder_signed, (-remainder_abs).asSInt, remainder_abs.asSInt)
when(io.src2 === 0.U) {

4
chisel/playground/src/pipeline/execute/fu/Mdu.scala
View File

@ -38,7 +38,7 @@ class Mdu(implicit cpuConfig: CpuConfig) extends Module {
mul.src1 := LookupTree(op(1, 0), srcMulConvertTable.map(p => (p._1, p._2._1(src1))))
mul.src2 := LookupTree(op(1, 0), srcMulConvertTable.map(p => (p._1, p._2._2(src2))))
mul.start := valid && !is_div
mul.en := valid && !is_div
mul.allow_to_go := io.allow_to_go
val srcDivConvertFunc = (x: UInt) =>
@ -46,7 +46,7 @@ class Mdu(implicit cpuConfig: CpuConfig) extends Module {
div.src1 := srcDivConvertFunc(src1)
div.src2 := srcDivConvertFunc(src2)
div.signed := MDUOpType.isDivSign(op)
div.start := valid && is_div
div.en := valid && is_div
div.allow_to_go := io.allow_to_go
val mul_result = Mux(op(1, 0) === MDUOpType.mul, mul.result(XLEN - 1, 0), mul.result(2 * XLEN - 1, XLEN))

14
chisel/playground/src/pipeline/execute/fu/Mul.scala
View File

@ -21,7 +21,7 @@ class Mul(implicit val cpuConfig: CpuConfig) extends Module {
val io = IO(new Bundle {
val src1 = Input(UInt((XLEN + 1).W))
val src2 = Input(UInt((XLEN + 1).W))
val start = Input(Bool())
val en = Input(Bool())
val allow_to_go = Input(Bool())
val ready = Output(Bool())
@ -36,13 +36,13 @@ class Mul(implicit val cpuConfig: CpuConfig) extends Module {
cnt := MuxCase(
cnt,
Seq(
(io.start && !io.ready) -> (cnt + 1.U),
io.allow_to_go -> 0.U
(io.en && !io.ready) -> (cnt + 1.U),
io.allow_to_go -> 0.U
)
)
signedMul.CLK := clock
signedMul.CE := io.start
signedMul.CE := io.en
signedMul.A := io.src1
signedMul.B := io.src2
@ -53,13 +53,13 @@ class Mul(implicit val cpuConfig: CpuConfig) extends Module {
cnt := MuxCase(
cnt,
Seq(
(io.start && !io.ready) -> (cnt + 1.U),
io.allow_to_go -> 0.U
(io.en && !io.ready) -> (cnt + 1.U),
io.allow_to_go -> 0.U
)
)
val signed = RegInit(0.U((2 * XLEN).W))
when(io.start) {
when(io.en) {
signed := (io.src1.asSInt * io.src2.asSInt).asUInt
}
io.result := signed