instinfo改为info

chisel/playground/src/defines/Bundles.scala

@@ -29,7 +29,7 @@ class RdInfo extends Bundle {
   val wdata = Vec(FuType.num, UInt(XLEN.W))
 }
 
-class InstInfo extends Bundle {
+class Info extends Bundle {
   val valid      = Bool()
   val inst_legal = Bool()
   val src1_ren   = Bool()

chisel/playground/src/defines/isa/Instructions.scala

@@ -156,7 +156,7 @@ object MDUOpType {
 
   def isDiv(op:     UInt) = op(2)
   def isDivSign(op: UInt) = isDiv(op) && !op(0)
-  def isW(op:       UInt) = op(3)
+  def isWordOp(op:  UInt) = op(3)
 }
 
 // csr unit

chisel/playground/src/pipeline/decode/DecodeUnit.scala

@@ -28,7 +28,7 @@ class DataForwardToDecodeUnit extends Bundle {
 class DecoderBranchPredictorUnit extends Bundle {
   val bpuConfig = new BranchPredictorConfig()
   val pc        = Output(UInt(XLEN.W))
-  val info      = Output(new InstInfo())
+  val info      = Output(new Info())
   val pht_index = Output(UInt(bpuConfig.phtDepth.W))
 
   val branch_inst      = Input(Bool())
@@ -61,7 +61,7 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep
 
   val pc   = io.instFifo.inst.map(_.pc)
   val inst = io.instFifo.inst.map(_.inst)
-  val info = Wire(Vec(cpuConfig.decoderNum, new InstInfo()))
+  val info = Wire(Vec(cpuConfig.decoderNum, new Info()))
   val mode = io.csr.mode
 
   info          := decoder.map(_.io.out.info)

chisel/playground/src/pipeline/decode/Decoder.scala

@@ -13,7 +13,7 @@ class Decoder extends Module with HasInstrType with HasCSRConst {
     })
     // outputs
     val out = Output(new Bundle {
-      val info = new InstInfo()
+      val info = new Info()
     })
   })
 

chisel/playground/src/pipeline/decode/Issue.scala

@@ -15,7 +15,7 @@ class Issue(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
       val empty        = Bool()
       val almost_empty = Bool()
     })
-    val decodeInst = Input(Vec(cpuConfig.decoderNum, new InstInfo()))
+    val decodeInst = Input(Vec(cpuConfig.decoderNum, new Info()))
     val execute    = Input(Vec(cpuConfig.commitNum, new MemRead()))
     // 输出
     val inst1 = Output(new Bundle {

chisel/playground/src/pipeline/decode/JumpCtrl.scala

@@ -11,7 +11,7 @@ class JumpCtrl(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val in = Input(new Bundle {
       val pc       = UInt(XLEN.W)
-      val info     = new InstInfo()
+      val info     = new Info()
       val src_info = new SrcInfo()
       val forward  = Vec(cpuConfig.commitNum, new DataForwardToDecodeUnit())
     })

chisel/playground/src/pipeline/execute/ExecuteStage.scala

@@ -9,7 +9,7 @@ import cpu.CpuConfig
 
 class IdExeData extends Bundle {
   val pc       = UInt(XLEN.W)
-  val info     = new InstInfo()
+  val info     = new Info()
   val src_info = new SrcInfo()
   val ex       = new ExceptionInfo()
 }

chisel/playground/src/pipeline/execute/Fu.scala

@@ -13,7 +13,7 @@ class Fu(implicit val cpuConfig: CpuConfig) extends Module {
       cpuConfig.decoderNum,
       new Bundle {
         val pc       = Input(UInt(XLEN.W))
-        val info     = Input(new InstInfo())
+        val info     = Input(new Info())
         val src_info = Input(new SrcInfo())
         val result = Output(new Bundle {
           val mdu = UInt(XLEN.W)
@@ -51,7 +51,7 @@ class Fu(implicit val cpuConfig: CpuConfig) extends Module {
   io.branch.target := branchCtrl.out.target
 
   for (i <- 0 until (cpuConfig.commitNum)) {
-    alu(i).io.info     := Mux(io.inst(i).info.fusel === FuType.alu, io.inst(i).info, 0.U.asTypeOf(new InstInfo()))
+    alu(i).io.info     := Mux(io.inst(i).info.fusel === FuType.alu, io.inst(i).info, 0.U.asTypeOf(new Info()))
     alu(i).io.src_info := Mux(io.inst(i).info.fusel === FuType.alu, io.inst(i).src_info, 0.U.asTypeOf(new SrcInfo()))
   }
 
@@ -61,7 +61,7 @@ class Fu(implicit val cpuConfig: CpuConfig) extends Module {
   )
 
   mdu.info := MuxCase(
-    0.U.asTypeOf(new InstInfo()),
+    0.U.asTypeOf(new Info()),
     Seq(mdu_sel(0) -> io.inst(0).info, mdu_sel(1) -> io.inst(1).info)
   )
   mdu.src_info := MuxCase(

chisel/playground/src/pipeline/execute/fu/Alu.scala

@@ -7,7 +7,7 @@ import cpu.defines.Const._
 
 class Alu extends Module {
   val io = IO(new Bundle {
-    val info     = Input(new InstInfo())
+    val info     = Input(new Info())
     val src_info = Input(new SrcInfo())
     val result   = Output(UInt(XLEN.W))
   })

chisel/playground/src/pipeline/execute/fu/BranchCtrl.scala

@@ -9,7 +9,7 @@ class BranchCtrl extends Module {
   val io = IO(new Bundle {
     val in = new Bundle {
       val pc            = Input(UInt(XLEN.W))
-      val info          = Input(new InstInfo())
+      val info          = Input(new Info())
       val src_info      = Input(new SrcInfo())
       val pred_branch   = Input(Bool())
       val jump_regiser  = Input(Bool())

chisel/playground/src/pipeline/execute/fu/Csr.scala

@@ -11,7 +11,7 @@ class CsrMemoryUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
   val in = Input(new Bundle {
     val pc   = UInt(XLEN.W)
     val ex   = new ExceptionInfo()
-    val info = new InstInfo()
+    val info = new Info()
 
     val lr_wen   = Bool()
     val lr_wbit  = Bool()
@@ -30,7 +30,7 @@ class CsrExecuteUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
   val in = Input(new Bundle {
     val valid    = Bool()
     val pc       = UInt(XLEN.W)
-    val info     = new InstInfo()
+    val info     = new Info()
     val src_info = new SrcInfo()
     val ex       = new ExceptionInfo()
   })

chisel/playground/src/pipeline/execute/fu/Mdu.scala

@@ -8,7 +8,7 @@ import cpu.CpuConfig
 
 class Mdu(implicit cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
-    val info        = Input(new InstInfo())
+    val info        = Input(new Info())
     val src_info    = Input(new SrcInfo())
     val allow_to_go = Input(Bool())
 
@@ -22,7 +22,7 @@ class Mdu(implicit cpuConfig: CpuConfig) extends Module {
   val valid  = io.info.valid
   val op     = io.info.op
   val is_div = MDUOpType.isDiv(op)
-  val is_w   = MDUOpType.isW(op)
+  val is_w   = MDUOpType.isWordOp(op)
 
   val src1 = io.src_info.src1_data
   val src2 = io.src_info.src2_data

chisel/playground/src/pipeline/memory/Lsu.scala

@@ -27,7 +27,7 @@ class Lsu_DataMemory extends Bundle {
 class Lsu_MemoryUnit extends Bundle {
   val in = Input(new Bundle {
     val mem_en   = Bool()
-    val info     = new InstInfo()
+    val info     = new Info()
     val src_info = new SrcInfo()
     val ex       = new ExceptionInfo()
 

chisel/playground/src/pipeline/memory/MemoryStage.scala

@@ -8,7 +8,7 @@ import cpu.CpuConfig
 
 class ExeMemData extends Bundle {
   val pc       = UInt(XLEN.W)
-  val info     = new InstInfo()
+  val info     = new Info()
   val rd_info  = new RdInfo()
   val src_info = new SrcInfo()
   val ex       = new ExceptionInfo()

chisel/playground/src/pipeline/memory/MemoryUnit.scala

@@ -54,7 +54,7 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
 
   io.csr.in.pc   := 0.U
   io.csr.in.ex   := 0.U.asTypeOf(new ExceptionInfo())
-  io.csr.in.info := 0.U.asTypeOf(new InstInfo())
+  io.csr.in.info := 0.U.asTypeOf(new Info())
 
   def selectInstField[T <: Data](select: Bool, fields: Seq[T]): T = {
     Mux1H(Seq(select -> fields(0), !select -> fields(1)))

chisel/playground/src/pipeline/memory/Mou.scala

@@ -8,7 +8,7 @@ import cpu.defines.Const._
 class Mou extends Module {
   val io = IO(new Bundle {
     val in = Input(new Bundle {
-      val info = new InstInfo()
+      val info = new Info()
       val pc   = UInt(XLEN.W)
     })
     val out = Output(new Bundle {

chisel/playground/src/pipeline/memory/lsu/AtomAlu.scala

@@ -11,7 +11,7 @@ class AtomAlu extends Module {
     val in = Input(new Bundle {
       val rdata = Input(UInt(XLEN.W)) // load data
       val src2  = Input(UInt(XLEN.W)) // reg data
-      val info  = new InstInfo()
+      val info  = new Info()
     })
     val out = Output(new Bundle {
       val result = Output(UInt(XLEN.W))

chisel/playground/src/pipeline/memory/lsu/LsExecute.scala

@@ -13,7 +13,7 @@ class LsExecute extends Module {
       val mem_en   = Bool()
       val mem_addr = UInt(XLEN.W)
       val wdata    = UInt(XLEN.W)
-      val info     = new InstInfo()
+      val info     = new Info()
     })
     val out = Output(new Bundle {
       val addr_misaligned = Bool()

chisel/playground/src/pipeline/writeback/WriteBackStage.scala

@@ -8,7 +8,7 @@ import cpu.CpuConfig
 
 class MemWbData extends Bundle {
   val pc      = UInt(XLEN.W)
-  val info    = new InstInfo()
+  val info    = new Info()
   val rd_info = new RdInfo()
   val ex      = new ExceptionInfo()
 }