From 678710a80daab1b61d4731d9696eb6af4f5231ef Mon Sep 17 00:00:00 2001 From: Liphen Date: Sat, 27 Jan 2024 17:20:27 +0800 Subject: [PATCH] =?UTF-8?q?instinfo=E6=94=B9=E4=B8=BAinfo?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/defines/Bundles.scala | 2 +- chisel/playground/src/defines/isa/Instructions.scala | 2 +- chisel/playground/src/pipeline/decode/DecodeUnit.scala | 4 ++-- chisel/playground/src/pipeline/decode/Decoder.scala | 2 +- chisel/playground/src/pipeline/decode/Issue.scala | 2 +- chisel/playground/src/pipeline/decode/JumpCtrl.scala | 2 +- chisel/playground/src/pipeline/execute/ExecuteStage.scala | 2 +- chisel/playground/src/pipeline/execute/Fu.scala | 6 +++--- chisel/playground/src/pipeline/execute/fu/Alu.scala | 2 +- chisel/playground/src/pipeline/execute/fu/BranchCtrl.scala | 2 +- chisel/playground/src/pipeline/execute/fu/Csr.scala | 4 ++-- chisel/playground/src/pipeline/execute/fu/Mdu.scala | 4 ++-- chisel/playground/src/pipeline/memory/Lsu.scala | 2 +- chisel/playground/src/pipeline/memory/MemoryStage.scala | 2 +- chisel/playground/src/pipeline/memory/MemoryUnit.scala | 2 +- chisel/playground/src/pipeline/memory/Mou.scala | 2 +- chisel/playground/src/pipeline/memory/lsu/AtomAlu.scala | 2 +- chisel/playground/src/pipeline/memory/lsu/LsExecute.scala | 2 +- .../playground/src/pipeline/writeback/WriteBackStage.scala | 2 +- 19 files changed, 24 insertions(+), 24 deletions(-) diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala index 4490504..0f15353 100644 --- a/chisel/playground/src/defines/Bundles.scala +++ b/chisel/playground/src/defines/Bundles.scala @@ -29,7 +29,7 @@ class RdInfo extends Bundle { val wdata = Vec(FuType.num, UInt(XLEN.W)) } -class InstInfo extends Bundle { +class Info extends Bundle { val valid = Bool() val inst_legal = Bool() val src1_ren = Bool() diff --git a/chisel/playground/src/defines/isa/Instructions.scala b/chisel/playground/src/defines/isa/Instructions.scala index 8f6e95f..b32ab56 100644 --- a/chisel/playground/src/defines/isa/Instructions.scala +++ b/chisel/playground/src/defines/isa/Instructions.scala @@ -156,7 +156,7 @@ object MDUOpType { def isDiv(op: UInt) = op(2) def isDivSign(op: UInt) = isDiv(op) && !op(0) - def isW(op: UInt) = op(3) + def isWordOp(op: UInt) = op(3) } // csr unit diff --git a/chisel/playground/src/pipeline/decode/DecodeUnit.scala b/chisel/playground/src/pipeline/decode/DecodeUnit.scala index a9db7fd..444c4e2 100644 --- a/chisel/playground/src/pipeline/decode/DecodeUnit.scala +++ b/chisel/playground/src/pipeline/decode/DecodeUnit.scala @@ -28,7 +28,7 @@ class DataForwardToDecodeUnit extends Bundle { class DecoderBranchPredictorUnit extends Bundle { val bpuConfig = new BranchPredictorConfig() val pc = Output(UInt(XLEN.W)) - val info = Output(new InstInfo()) + val info = Output(new Info()) val pht_index = Output(UInt(bpuConfig.phtDepth.W)) val branch_inst = Input(Bool()) @@ -61,7 +61,7 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep val pc = io.instFifo.inst.map(_.pc) val inst = io.instFifo.inst.map(_.inst) - val info = Wire(Vec(cpuConfig.decoderNum, new InstInfo())) + val info = Wire(Vec(cpuConfig.decoderNum, new Info())) val mode = io.csr.mode info := decoder.map(_.io.out.info) diff --git a/chisel/playground/src/pipeline/decode/Decoder.scala b/chisel/playground/src/pipeline/decode/Decoder.scala index d64adaa..b0e11ee 100644 --- a/chisel/playground/src/pipeline/decode/Decoder.scala +++ b/chisel/playground/src/pipeline/decode/Decoder.scala @@ -13,7 +13,7 @@ class Decoder extends Module with HasInstrType with HasCSRConst { }) // outputs val out = Output(new Bundle { - val info = new InstInfo() + val info = new Info() }) }) diff --git a/chisel/playground/src/pipeline/decode/Issue.scala b/chisel/playground/src/pipeline/decode/Issue.scala index 044593f..2857aec 100644 --- a/chisel/playground/src/pipeline/decode/Issue.scala +++ b/chisel/playground/src/pipeline/decode/Issue.scala @@ -15,7 +15,7 @@ class Issue(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst { val empty = Bool() val almost_empty = Bool() }) - val decodeInst = Input(Vec(cpuConfig.decoderNum, new InstInfo())) + val decodeInst = Input(Vec(cpuConfig.decoderNum, new Info())) val execute = Input(Vec(cpuConfig.commitNum, new MemRead())) // 输出 val inst1 = Output(new Bundle { diff --git a/chisel/playground/src/pipeline/decode/JumpCtrl.scala b/chisel/playground/src/pipeline/decode/JumpCtrl.scala index c1570a6..8f14765 100644 --- a/chisel/playground/src/pipeline/decode/JumpCtrl.scala +++ b/chisel/playground/src/pipeline/decode/JumpCtrl.scala @@ -11,7 +11,7 @@ class JumpCtrl(implicit val cpuConfig: CpuConfig) extends Module { val io = IO(new Bundle { val in = Input(new Bundle { val pc = UInt(XLEN.W) - val info = new InstInfo() + val info = new Info() val src_info = new SrcInfo() val forward = Vec(cpuConfig.commitNum, new DataForwardToDecodeUnit()) }) diff --git a/chisel/playground/src/pipeline/execute/ExecuteStage.scala b/chisel/playground/src/pipeline/execute/ExecuteStage.scala index fe4e823..1a11da2 100644 --- a/chisel/playground/src/pipeline/execute/ExecuteStage.scala +++ b/chisel/playground/src/pipeline/execute/ExecuteStage.scala @@ -9,7 +9,7 @@ import cpu.CpuConfig class IdExeData extends Bundle { val pc = UInt(XLEN.W) - val info = new InstInfo() + val info = new Info() val src_info = new SrcInfo() val ex = new ExceptionInfo() } diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala index cbf8267..7f1addc 100644 --- a/chisel/playground/src/pipeline/execute/Fu.scala +++ b/chisel/playground/src/pipeline/execute/Fu.scala @@ -13,7 +13,7 @@ class Fu(implicit val cpuConfig: CpuConfig) extends Module { cpuConfig.decoderNum, new Bundle { val pc = Input(UInt(XLEN.W)) - val info = Input(new InstInfo()) + val info = Input(new Info()) val src_info = Input(new SrcInfo()) val result = Output(new Bundle { val mdu = UInt(XLEN.W) @@ -51,7 +51,7 @@ class Fu(implicit val cpuConfig: CpuConfig) extends Module { io.branch.target := branchCtrl.out.target for (i <- 0 until (cpuConfig.commitNum)) { - alu(i).io.info := Mux(io.inst(i).info.fusel === FuType.alu, io.inst(i).info, 0.U.asTypeOf(new InstInfo())) + alu(i).io.info := Mux(io.inst(i).info.fusel === FuType.alu, io.inst(i).info, 0.U.asTypeOf(new Info())) alu(i).io.src_info := Mux(io.inst(i).info.fusel === FuType.alu, io.inst(i).src_info, 0.U.asTypeOf(new SrcInfo())) } @@ -61,7 +61,7 @@ class Fu(implicit val cpuConfig: CpuConfig) extends Module { ) mdu.info := MuxCase( - 0.U.asTypeOf(new InstInfo()), + 0.U.asTypeOf(new Info()), Seq(mdu_sel(0) -> io.inst(0).info, mdu_sel(1) -> io.inst(1).info) ) mdu.src_info := MuxCase( diff --git a/chisel/playground/src/pipeline/execute/fu/Alu.scala b/chisel/playground/src/pipeline/execute/fu/Alu.scala index 27b7bc1..46962b6 100644 --- a/chisel/playground/src/pipeline/execute/fu/Alu.scala +++ b/chisel/playground/src/pipeline/execute/fu/Alu.scala @@ -7,7 +7,7 @@ import cpu.defines.Const._ class Alu extends Module { val io = IO(new Bundle { - val info = Input(new InstInfo()) + val info = Input(new Info()) val src_info = Input(new SrcInfo()) val result = Output(UInt(XLEN.W)) }) diff --git a/chisel/playground/src/pipeline/execute/fu/BranchCtrl.scala b/chisel/playground/src/pipeline/execute/fu/BranchCtrl.scala index fcc4e84..bd3113a 100644 --- a/chisel/playground/src/pipeline/execute/fu/BranchCtrl.scala +++ b/chisel/playground/src/pipeline/execute/fu/BranchCtrl.scala @@ -9,7 +9,7 @@ class BranchCtrl extends Module { val io = IO(new Bundle { val in = new Bundle { val pc = Input(UInt(XLEN.W)) - val info = Input(new InstInfo()) + val info = Input(new Info()) val src_info = Input(new SrcInfo()) val pred_branch = Input(Bool()) val jump_regiser = Input(Bool()) diff --git a/chisel/playground/src/pipeline/execute/fu/Csr.scala b/chisel/playground/src/pipeline/execute/fu/Csr.scala index dc0bf00..6a9a14c 100644 --- a/chisel/playground/src/pipeline/execute/fu/Csr.scala +++ b/chisel/playground/src/pipeline/execute/fu/Csr.scala @@ -11,7 +11,7 @@ class CsrMemoryUnit(implicit val cpuConfig: CpuConfig) extends Bundle { val in = Input(new Bundle { val pc = UInt(XLEN.W) val ex = new ExceptionInfo() - val info = new InstInfo() + val info = new Info() val lr_wen = Bool() val lr_wbit = Bool() @@ -30,7 +30,7 @@ class CsrExecuteUnit(implicit val cpuConfig: CpuConfig) extends Bundle { val in = Input(new Bundle { val valid = Bool() val pc = UInt(XLEN.W) - val info = new InstInfo() + val info = new Info() val src_info = new SrcInfo() val ex = new ExceptionInfo() }) diff --git a/chisel/playground/src/pipeline/execute/fu/Mdu.scala b/chisel/playground/src/pipeline/execute/fu/Mdu.scala index b3941d0..62b2dd8 100644 --- a/chisel/playground/src/pipeline/execute/fu/Mdu.scala +++ b/chisel/playground/src/pipeline/execute/fu/Mdu.scala @@ -8,7 +8,7 @@ import cpu.CpuConfig class Mdu(implicit cpuConfig: CpuConfig) extends Module { val io = IO(new Bundle { - val info = Input(new InstInfo()) + val info = Input(new Info()) val src_info = Input(new SrcInfo()) val allow_to_go = Input(Bool()) @@ -22,7 +22,7 @@ class Mdu(implicit cpuConfig: CpuConfig) extends Module { val valid = io.info.valid val op = io.info.op val is_div = MDUOpType.isDiv(op) - val is_w = MDUOpType.isW(op) + val is_w = MDUOpType.isWordOp(op) val src1 = io.src_info.src1_data val src2 = io.src_info.src2_data diff --git a/chisel/playground/src/pipeline/memory/Lsu.scala b/chisel/playground/src/pipeline/memory/Lsu.scala index 88a0c61..2b0e466 100644 --- a/chisel/playground/src/pipeline/memory/Lsu.scala +++ b/chisel/playground/src/pipeline/memory/Lsu.scala @@ -27,7 +27,7 @@ class Lsu_DataMemory extends Bundle { class Lsu_MemoryUnit extends Bundle { val in = Input(new Bundle { val mem_en = Bool() - val info = new InstInfo() + val info = new Info() val src_info = new SrcInfo() val ex = new ExceptionInfo() diff --git a/chisel/playground/src/pipeline/memory/MemoryStage.scala b/chisel/playground/src/pipeline/memory/MemoryStage.scala index 1e6a89c..59833b1 100644 --- a/chisel/playground/src/pipeline/memory/MemoryStage.scala +++ b/chisel/playground/src/pipeline/memory/MemoryStage.scala @@ -8,7 +8,7 @@ import cpu.CpuConfig class ExeMemData extends Bundle { val pc = UInt(XLEN.W) - val info = new InstInfo() + val info = new Info() val rd_info = new RdInfo() val src_info = new SrcInfo() val ex = new ExceptionInfo() diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala index 7a8fbf3..f66f02b 100644 --- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala +++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala @@ -54,7 +54,7 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module { io.csr.in.pc := 0.U io.csr.in.ex := 0.U.asTypeOf(new ExceptionInfo()) - io.csr.in.info := 0.U.asTypeOf(new InstInfo()) + io.csr.in.info := 0.U.asTypeOf(new Info()) def selectInstField[T <: Data](select: Bool, fields: Seq[T]): T = { Mux1H(Seq(select -> fields(0), !select -> fields(1))) diff --git a/chisel/playground/src/pipeline/memory/Mou.scala b/chisel/playground/src/pipeline/memory/Mou.scala index 03533d6..cc7711d 100644 --- a/chisel/playground/src/pipeline/memory/Mou.scala +++ b/chisel/playground/src/pipeline/memory/Mou.scala @@ -8,7 +8,7 @@ import cpu.defines.Const._ class Mou extends Module { val io = IO(new Bundle { val in = Input(new Bundle { - val info = new InstInfo() + val info = new Info() val pc = UInt(XLEN.W) }) val out = Output(new Bundle { diff --git a/chisel/playground/src/pipeline/memory/lsu/AtomAlu.scala b/chisel/playground/src/pipeline/memory/lsu/AtomAlu.scala index 1f3ffc0..2206b13 100644 --- a/chisel/playground/src/pipeline/memory/lsu/AtomAlu.scala +++ b/chisel/playground/src/pipeline/memory/lsu/AtomAlu.scala @@ -11,7 +11,7 @@ class AtomAlu extends Module { val in = Input(new Bundle { val rdata = Input(UInt(XLEN.W)) // load data val src2 = Input(UInt(XLEN.W)) // reg data - val info = new InstInfo() + val info = new Info() }) val out = Output(new Bundle { val result = Output(UInt(XLEN.W)) diff --git a/chisel/playground/src/pipeline/memory/lsu/LsExecute.scala b/chisel/playground/src/pipeline/memory/lsu/LsExecute.scala index e06b04a..dbda744 100644 --- a/chisel/playground/src/pipeline/memory/lsu/LsExecute.scala +++ b/chisel/playground/src/pipeline/memory/lsu/LsExecute.scala @@ -13,7 +13,7 @@ class LsExecute extends Module { val mem_en = Bool() val mem_addr = UInt(XLEN.W) val wdata = UInt(XLEN.W) - val info = new InstInfo() + val info = new Info() }) val out = Output(new Bundle { val addr_misaligned = Bool() diff --git a/chisel/playground/src/pipeline/writeback/WriteBackStage.scala b/chisel/playground/src/pipeline/writeback/WriteBackStage.scala index 68b638b..53c9a3e 100644 --- a/chisel/playground/src/pipeline/writeback/WriteBackStage.scala +++ b/chisel/playground/src/pipeline/writeback/WriteBackStage.scala @@ -8,7 +8,7 @@ import cpu.CpuConfig class MemWbData extends Bundle { val pc = UInt(XLEN.W) - val info = new InstInfo() + val info = new Info() val rd_info = new RdInfo() val ex = new ExceptionInfo() }