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重构instfifo

This commit is contained in:
Liphen 2024-01-23 14:38:47 +08:00
parent 8b4f9c71dd
commit 9c3e70a3f4
6 changed files with 45 additions and 45 deletions
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5
chisel/playground/src/Core.scala
View File

@ -63,8 +63,7 @@ class Core(implicit val cpuConfig: CpuConfig) extends Module {
bpu.execute <> executeUnit.bpu
instFifo.do_flush := ctrl.decodeUnit.do_flush
instFifo.ren <> decodeUnit.instFifo.allow_to_go
decodeUnit.instFifo.inst <> instFifo.read
instFifo.decoderUint <> decodeUnit.instFifo
for (i <- 0 until cpuConfig.instFetchNum) {
instFifo.write(i).pht_index := bpu.instBuffer.pht_index(i)
@ -76,8 +75,6 @@ class Core(implicit val cpuConfig: CpuConfig) extends Module {
instFifo.write(i).page_fault := io.inst.page_fault
}
decodeUnit.instFifo.info.empty := instFifo.empty
decodeUnit.instFifo.info.almost_empty := instFifo.almost_empty
decodeUnit.regfile <> regfile.read
for (i <- 0 until (cpuConfig.commitNum)) {
decodeUnit.forward(i).exe := executeUnit.decodeUnit.forward(i).exe

10
chisel/playground/src/pipeline/decode/DecodeUnit.scala
View File

@ -7,12 +7,12 @@ import cpu.defines._
import cpu.defines.Const._
import cpu.{BranchPredictorConfig, CpuConfig}
import cpu.pipeline.execute.DecodeUnitExecuteUnit
import cpu.pipeline.fetch.BufferUnit
import cpu.pipeline.fetch.IfIdData
import cpu.pipeline.execute
class DecodeUnitInstFifo(implicit val cpuConfig: CpuConfig) extends Bundle {
val allow_to_go = Output(Vec(cpuConfig.decoderNum, Bool()))
val inst = Input(Vec(cpuConfig.decoderNum, new BufferUnit()))
val inst = Input(Vec(cpuConfig.decoderNum, new IfIdData()))
val info = Input(new Bundle {
val empty = Bool()
val almost_empty = Bool()
@ -20,9 +20,9 @@ class DecodeUnitInstFifo(implicit val cpuConfig: CpuConfig) extends Bundle {
}
class DataForwardToDecodeUnit extends Bundle {
val exe = new RegWrite()
val exe = new RegWrite()
val is_load = Bool()
val mem = new RegWrite()
val mem = new RegWrite()
}
class DecoderBranchPredictorUnit extends Bundle {
@ -74,7 +74,7 @@ class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExcep
for (i <- 0 until (cpuConfig.decoderNum)) {
decoder(i).io.in.inst := inst(i)
issue.decodeInst(i) := info(i)
issue.execute(i).is_load := io.forward(i).is_load
issue.execute(i).is_load := io.forward(i).is_load
issue.execute(i).reg_waddr := io.forward(i).exe.waddr
io.regfile(i).src1.raddr := info(i).src1_raddr
io.regfile(i).src2.raddr := info(i).src2_raddr

16
chisel/playground/src/pipeline/execute/ExecuteStage.scala
View File

@ -7,14 +7,14 @@ import cpu.defines.Const._
import cpu.{BranchPredictorConfig, CpuConfig}
import cpu.CpuConfig
class IdExeInfo extends Bundle {
class IdExeData extends Bundle {
val pc = UInt(XLEN.W)
val info = new InstInfo()
val src_info = new SrcInfo()
val ex = new ExceptionInfo()
}
class JumpBranchInfo extends Bundle {
class JumpBranchData extends Bundle {
val jump_regiser = Bool()
val branch_inst = Bool()
val pred_branch = Bool()
@ -23,8 +23,8 @@ class JumpBranchInfo extends Bundle {
}
class DecodeUnitExecuteUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
val inst = Vec(cpuConfig.commitNum, new IdExeInfo())
val jump_branch_info = new JumpBranchInfo()
val inst = Vec(cpuConfig.commitNum, new IdExeData())
val jump_branch_info = new JumpBranchData()
}
class ExecuteStage(implicit val cpuConfig: CpuConfig) extends Module {
@ -37,12 +37,12 @@ class ExecuteStage(implicit val cpuConfig: CpuConfig) extends Module {
val executeUnit = Output(new DecodeUnitExecuteUnit())
})
val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new IdExeInfo())))
val jump_branch_info = RegInit(0.U.asTypeOf(new JumpBranchInfo()))
val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new IdExeData())))
val jump_branch_info = RegInit(0.U.asTypeOf(new JumpBranchData()))
for (i <- 0 until (cpuConfig.commitNum)) {
when(io.ctrl.clear(i)) {
inst(i) := 0.U.asTypeOf(new IdExeInfo())
inst(i) := 0.U.asTypeOf(new IdExeData())
}.elsewhen(io.ctrl.allow_to_go(i)) {
inst(i) := io.decodeUnit.inst(i)
}
@ -50,7 +50,7 @@ class ExecuteStage(implicit val cpuConfig: CpuConfig) extends Module {
// inst0携带分支预测相关信息
when(io.ctrl.clear(0)) {
jump_branch_info := 0.U.asTypeOf(new JumpBranchInfo())
jump_branch_info := 0.U.asTypeOf(new JumpBranchData())
}.elsewhen(io.ctrl.allow_to_go(0)) {
jump_branch_info := io.decodeUnit.jump_branch_info
}

43
chisel/playground/src/pipeline/fetch/InstFifo.scala
View File

@ -4,8 +4,9 @@ import chisel3._
import chisel3.util._
import cpu.defines.Const._
import cpu.{BranchPredictorConfig, CpuConfig}
import cpu.pipeline.decode.DecodeUnitInstFifo
class BufferUnit extends Bundle {
class IfIdData extends Bundle {
val bpuConfig = new BranchPredictorConfig()
val inst = UInt(XLEN.W)
val pht_index = UInt(bpuConfig.phtDepth.W)
@ -18,18 +19,14 @@ class InstFifo(implicit val cpuConfig: CpuConfig) extends Module {
val io = IO(new Bundle {
val do_flush = Input(Bool())
val ren = Input(Vec(cpuConfig.decoderNum, Bool()))
val read = Output(Vec(cpuConfig.decoderNum, new BufferUnit()))
val wen = Input(Vec(cpuConfig.instFetchNum, Bool()))
val write = Input(Vec(cpuConfig.instFetchNum, new BufferUnit()))
val write = Input(Vec(cpuConfig.instFetchNum, new IfIdData()))
val full = Output(Bool())
val empty = Output(Bool())
val almost_empty = Output(Bool())
val full = Output(Bool())
val decoderUint = Flipped(new DecodeUnitInstFifo())
})
// fifo buffer
val buffer = RegInit(VecInit(Seq.fill(cpuConfig.instFifoDepth)(0.U.asTypeOf(new BufferUnit()))))
val buffer = RegInit(VecInit(Seq.fill(cpuConfig.instFifoDepth)(0.U.asTypeOf(new IfIdData()))))
// fifo ptr
val enq_ptr = RegInit(0.U(log2Ceil(cpuConfig.instFifoDepth).W))
@ -38,31 +35,37 @@ class InstFifo(implicit val cpuConfig: CpuConfig) extends Module {
// config.instFifoDepth - 1 is the last element, config.instFifoDepth - 2 is the last second element
// the second last element's valid decide whether the fifo is full
io.full := count >= (cpuConfig.instFifoDepth - cpuConfig.instFetchNum).U // TODO:这里的等于号还可以优化
io.empty := count === 0.U
io.almost_empty := count === 1.U
val full = count >= (cpuConfig.instFifoDepth - cpuConfig.instFetchNum).U
val empty = count === 0.U
val almost_empty = count === 1.U
io.full := full
io.decoderUint.info.empty := empty
io.decoderUint.info.almost_empty := almost_empty
// * deq * //
io.read(0) := MuxCase(
io.decoderUint.inst(0) := MuxCase(
buffer(deq_ptr),
Seq(
io.empty -> 0.U.asTypeOf(new BufferUnit()),
io.almost_empty -> buffer(deq_ptr)
empty -> 0.U.asTypeOf(new IfIdData()),
almost_empty -> buffer(deq_ptr)
)
)
io.read(1) := MuxCase(
io.decoderUint.inst(1) := MuxCase(
buffer(deq_ptr + 1.U),
Seq(
(io.empty || io.almost_empty) -> 0.U.asTypeOf(new BufferUnit())
(empty || almost_empty) -> 0.U.asTypeOf(new IfIdData())
)
)
val deq_num = MuxCase(
0.U,
Seq(
(io.empty) -> 0.U,
io.ren(1) -> 2.U,
io.ren(0) -> 1.U
(empty) -> 0.U,
io.decoderUint.allow_to_go(1) -> 2.U,
io.decoderUint.allow_to_go(0) -> 1.U
)
)

8
chisel/playground/src/pipeline/memory/MemoryStage.scala
View File

@ -6,7 +6,7 @@ import cpu.defines._
import cpu.defines.Const._
import cpu.CpuConfig
class ExeMemInfo extends Bundle {
class ExeMemData extends Bundle {
val pc = UInt(XLEN.W)
val info = new InstInfo()
val rd_info = new RdInfo()
@ -15,7 +15,7 @@ class ExeMemInfo extends Bundle {
}
class ExecuteUnitMemoryUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
val inst = Vec(cpuConfig.commitNum, new ExeMemInfo())
val inst = Vec(cpuConfig.commitNum, new ExeMemData())
}
class MemoryStage(implicit val cpuConfig: CpuConfig) extends Module {
@ -27,11 +27,11 @@ class MemoryStage(implicit val cpuConfig: CpuConfig) extends Module {
val executeUnit = Input(new ExecuteUnitMemoryUnit())
val memoryUnit = Output(new ExecuteUnitMemoryUnit())
})
val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new ExeMemInfo())))
val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new ExeMemData())))
for (i <- 0 until (cpuConfig.commitNum)) {
when(io.ctrl.clear) {
inst(i) := 0.U.asTypeOf(new ExeMemInfo())
inst(i) := 0.U.asTypeOf(new ExeMemData())
}.elsewhen(io.ctrl.allow_to_go) {
inst(i) := io.executeUnit.inst(i)
}

8
chisel/playground/src/pipeline/writeback/WriteBackStage.scala
View File

@ -6,7 +6,7 @@ import cpu.defines._
import cpu.defines.Const._
import cpu.CpuConfig
class MemWbInfo extends Bundle {
class MemWbData extends Bundle {
val pc = UInt(XLEN.W)
val info = new InstInfo()
val rd_info = new RdInfo()
@ -14,7 +14,7 @@ class MemWbInfo extends Bundle {
}
class MemoryUnitWriteBackUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
val inst = Vec(cpuConfig.commitNum, new MemWbInfo())
val inst = Vec(cpuConfig.commitNum, new MemWbData())
}
class WriteBackStage(implicit val cpuConfig: CpuConfig) extends Module {
val io = IO(new Bundle {
@ -26,11 +26,11 @@ class WriteBackStage(implicit val cpuConfig: CpuConfig) extends Module {
val writeBackUnit = Output(new MemoryUnitWriteBackUnit())
})
val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new MemWbInfo())))
val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new MemWbData())))
for (i <- 0 until (cpuConfig.commitNum)) {
when(io.ctrl.clear) {
inst(i) := 0.U.asTypeOf(new MemWbInfo())
inst(i) := 0.U.asTypeOf(new MemWbData())
}.elsewhen(io.ctrl.allow_to_go) {
inst(i) := io.memoryUnit.inst(i)
}