refactor: 大致完成cpu的重构
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1effd2929a
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8b4f9c71dd
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@ -87,15 +87,13 @@ class Core(implicit val cpuConfig: CpuConfig) extends Module {
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decodeUnit.csr <> csr.decodeUnit
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decodeUnit.executeStage <> executeStage.decodeUnit
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executeStage.ctrl.clear(0) := ctrl.memoryUnit.flush ||
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for (i <- 0 until (cpuConfig.commitNum)) {
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executeStage.ctrl.clear(i) := ctrl.memoryUnit.flush ||
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ctrl.executeUnit.do_flush && ctrl.executeUnit.allow_to_go ||
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!ctrl.decodeUnit.allow_to_go && ctrl.executeUnit.allow_to_go
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executeStage.ctrl.clear(1) := ctrl.memoryUnit.flush ||
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ctrl.executeUnit.do_flush && decodeUnit.instFifo.allow_to_go(1) ||
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!decodeUnit.instFifo.allow_to_go(1) && ctrl.executeUnit.allow_to_go
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executeStage.ctrl.allow_to_go(0) := ctrl.executeUnit.allow_to_go
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executeStage.ctrl.allow_to_go(1) := decodeUnit.instFifo.allow_to_go(1)
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!decodeUnit.instFifo.allow_to_go(i) && ctrl.executeUnit.allow_to_go
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executeStage.ctrl.allow_to_go(i) := decodeUnit.instFifo.allow_to_go(i)
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}
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executeUnit.executeStage <> executeStage.executeUnit
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executeUnit.csr <> csr.executeUnit
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executeUnit.memoryStage <> memoryStage.executeUnit
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@ -23,7 +23,6 @@ class Ctrl(implicit val cpuConfig: CpuConfig) extends Module {
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(io.decodeUnit.inst0.src1.ren && io.decodeUnit.inst0.src1.raddr === io.executeUnit.inst(1).reg_waddr ||
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io.decodeUnit.inst0.src2.ren && io.decodeUnit.inst0.src2.raddr === io.executeUnit.inst(1).reg_waddr)
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val lw_stall = inst0_lw_stall || inst1_lw_stall
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// TODO: 这里的stall信号可以改进,尝试让前后端完全解耦
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val longest_stall =
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io.executeUnit.fu.stall || io.cacheCtrl.iCache_stall || io.memoryUnit.mem_stall
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