From 8b4f9c71dd2f7bc754a4433418ca7a4577a4d961 Mon Sep 17 00:00:00 2001 From: Liphen Date: Tue, 23 Jan 2024 13:08:06 +0800 Subject: [PATCH] =?UTF-8?q?refactor:=20=E5=A4=A7=E8=87=B4=E5=AE=8C?= =?UTF-8?q?=E6=88=90cpu=E7=9A=84=E9=87=8D=E6=9E=84?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/Core.scala | 12 +++++------- chisel/playground/src/ctrl/Ctrl.scala | 1 - 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala index 4ec921c..f3171b5 100644 --- a/chisel/playground/src/Core.scala +++ b/chisel/playground/src/Core.scala @@ -87,15 +87,13 @@ class Core(implicit val cpuConfig: CpuConfig) extends Module { decodeUnit.csr <> csr.decodeUnit decodeUnit.executeStage <> executeStage.decodeUnit - executeStage.ctrl.clear(0) := ctrl.memoryUnit.flush || + for (i <- 0 until (cpuConfig.commitNum)) { + executeStage.ctrl.clear(i) := ctrl.memoryUnit.flush || ctrl.executeUnit.do_flush && ctrl.executeUnit.allow_to_go || - !ctrl.decodeUnit.allow_to_go && ctrl.executeUnit.allow_to_go - executeStage.ctrl.clear(1) := ctrl.memoryUnit.flush || - ctrl.executeUnit.do_flush && decodeUnit.instFifo.allow_to_go(1) || - !decodeUnit.instFifo.allow_to_go(1) && ctrl.executeUnit.allow_to_go - executeStage.ctrl.allow_to_go(0) := ctrl.executeUnit.allow_to_go - executeStage.ctrl.allow_to_go(1) := decodeUnit.instFifo.allow_to_go(1) + !decodeUnit.instFifo.allow_to_go(i) && ctrl.executeUnit.allow_to_go + executeStage.ctrl.allow_to_go(i) := decodeUnit.instFifo.allow_to_go(i) + } executeUnit.executeStage <> executeStage.executeUnit executeUnit.csr <> csr.executeUnit executeUnit.memoryStage <> memoryStage.executeUnit diff --git a/chisel/playground/src/ctrl/Ctrl.scala b/chisel/playground/src/ctrl/Ctrl.scala index 0089aad..d9ddb8d 100644 --- a/chisel/playground/src/ctrl/Ctrl.scala +++ b/chisel/playground/src/ctrl/Ctrl.scala @@ -23,7 +23,6 @@ class Ctrl(implicit val cpuConfig: CpuConfig) extends Module { (io.decodeUnit.inst0.src1.ren && io.decodeUnit.inst0.src1.raddr === io.executeUnit.inst(1).reg_waddr || io.decodeUnit.inst0.src2.ren && io.decodeUnit.inst0.src2.raddr === io.executeUnit.inst(1).reg_waddr) val lw_stall = inst0_lw_stall || inst1_lw_stall - // TODO: 这里的stall信号可以改进，尝试让前后端完全解耦 val longest_stall = io.executeUnit.fu.stall || io.cacheCtrl.iCache_stall || io.memoryUnit.mem_stall