diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala
index 4ec921c..f3171b5 100644
--- a/chisel/playground/src/Core.scala
+++ b/chisel/playground/src/Core.scala
@@ -87,15 +87,13 @@ class Core(implicit val cpuConfig: CpuConfig) extends Module {
   decodeUnit.csr <> csr.decodeUnit
   decodeUnit.executeStage <> executeStage.decodeUnit
 
-  executeStage.ctrl.clear(0) := ctrl.memoryUnit.flush ||
+  for (i <- 0 until (cpuConfig.commitNum)) {
+    executeStage.ctrl.clear(i) := ctrl.memoryUnit.flush ||
     ctrl.executeUnit.do_flush && ctrl.executeUnit.allow_to_go ||
-    !ctrl.decodeUnit.allow_to_go && ctrl.executeUnit.allow_to_go
-  executeStage.ctrl.clear(1) := ctrl.memoryUnit.flush ||
-    ctrl.executeUnit.do_flush && decodeUnit.instFifo.allow_to_go(1) ||
-    !decodeUnit.instFifo.allow_to_go(1) && ctrl.executeUnit.allow_to_go
-  executeStage.ctrl.allow_to_go(0) := ctrl.executeUnit.allow_to_go
-  executeStage.ctrl.allow_to_go(1) := decodeUnit.instFifo.allow_to_go(1)
+    !decodeUnit.instFifo.allow_to_go(i) && ctrl.executeUnit.allow_to_go
 
+    executeStage.ctrl.allow_to_go(i) := decodeUnit.instFifo.allow_to_go(i)
+  }
   executeUnit.executeStage <> executeStage.executeUnit
   executeUnit.csr <> csr.executeUnit
   executeUnit.memoryStage <> memoryStage.executeUnit
diff --git a/chisel/playground/src/ctrl/Ctrl.scala b/chisel/playground/src/ctrl/Ctrl.scala
index 0089aad..d9ddb8d 100644
--- a/chisel/playground/src/ctrl/Ctrl.scala
+++ b/chisel/playground/src/ctrl/Ctrl.scala
@@ -23,7 +23,6 @@ class Ctrl(implicit val cpuConfig: CpuConfig) extends Module {
     (io.decodeUnit.inst0.src1.ren && io.decodeUnit.inst0.src1.raddr === io.executeUnit.inst(1).reg_waddr ||
       io.decodeUnit.inst0.src2.ren && io.decodeUnit.inst0.src2.raddr === io.executeUnit.inst(1).reg_waddr)
   val lw_stall = inst0_lw_stall || inst1_lw_stall
-  // TODO: 这里的stall信号可以改进，尝试让前后端完全解耦
   val longest_stall =
     io.executeUnit.fu.stall || io.cacheCtrl.iCache_stall || io.memoryUnit.mem_stall