Liphen
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5bd7124535
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feat(debug): 增加sram差分测试接口
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2024-05-11 11:40:26 +08:00 |
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Liphen
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4a9e3dc05f
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修改debug信号的wen为commit
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2024-05-09 19:16:02 +08:00 |
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Liphen
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e955c3d580
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更改CpuConfig
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2024-03-22 23:16:48 +08:00 |
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Liphen
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6508b72858
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修改包名，修改各单元逻辑
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2024-03-22 22:45:48 +08:00 |
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Liphen
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a69e4e907d
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删除不必要的文件
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2024-03-22 14:23:12 +08:00 |
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Liphen
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b782293dac
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refactor: 修改异常变量名称
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2024-03-11 20:03:33 +08:00 |
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Liphen
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32005bb3e2
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删去部分无用定义
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2024-03-11 19:46:55 +08:00 |
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Liphen
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68dd1be7ac
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refactor(csr): 修改特权指令的解码赋值
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2024-03-11 19:26:26 +08:00 |
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Liphen
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f7fb3c4677
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fix(icache): 当地址未对齐时不应访存
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2024-03-09 16:12:56 +08:00 |
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Liphen
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ea7ce1cab9
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增加lab11和lab12
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2024-02-01 13:39:14 +08:00 |
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Liphen
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678710a80d
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instinfo改为info
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2024-01-27 17:20:27 +08:00 |
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Liphen
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413a7e22d2
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重构exe unit
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2024-01-22 15:40:38 +08:00 |
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Liphen
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3277f13a3f
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tval增加非法指令来源
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2024-01-20 17:30:18 +08:00 |
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Liphen
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a99cf13f87
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tlb支持巨页
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2024-01-18 16:10:59 +08:00 |
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Liphen
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21b73762a5
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fix: ret相关指令只进行单发射
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2024-01-17 14:25:35 +08:00 |
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Liphen
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404e0d64e6
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使得ptw可以从cache中取数
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2024-01-16 17:15:20 +08:00 |
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Liphen
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b16eff1ba7
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增加lsu的例外处理
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2024-01-15 16:01:22 +08:00 |
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Liphen
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cd4345690b
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增加sfence.vma
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2024-01-15 14:59:55 +08:00 |
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Liphen
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2f3ff6e5dd
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完成除vma指令外的框架
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2024-01-15 13:36:44 +08:00 |
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Liphen
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3a3680fb02
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增加ptw的大致框架
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2024-01-14 17:20:16 +08:00 |
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Liphen
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07490e0f13
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搭了下itlb的框架
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2024-01-13 17:09:01 +08:00 |
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Liphen
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6ca4ffcd86
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refactor: 重构tlb
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2024-01-13 13:13:31 +08:00 |
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Liphen
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08def4d1a0
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refactor: decoder级重命名为decode
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2024-01-07 16:57:36 +08:00 |
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Liphen
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eeb076b060
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增加tlb相关常量定义
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2024-01-03 16:17:36 +08:00 |
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Liphen
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78ca79384e
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style: config统一为cpuConfig
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2024-01-03 14:29:19 +08:00 |
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Liphen
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f3d5b5cd1e
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refactor: 将所有的地址宽度调为XLEN
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2024-01-03 10:54:44 +08:00 |
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Liphen
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e81d0d2b8c
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feat(lsu): 实现amo指令
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2023-12-29 11:56:37 +08:00 |
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Liphen
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7470c6fb5f
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增加fence，修复dcache的一处bug
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2023-12-28 22:21:38 +08:00 |
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Liphen
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e6a6f250c9
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fix(exe): 在exe提前访存
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2023-12-25 21:19:31 +08:00 |
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Liphen
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108c529698
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fix(cache): 将save状态改成wait，更符合作用
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2023-12-25 15:45:30 +08:00 |
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Liphen
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ac6aefff8a
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style(tlb): 加上p的前缀表示物理地址
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2023-12-25 14:08:54 +08:00 |
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Liphen
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e1639e6f8b
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fix(tlb): 修复数据宽度问题
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2023-12-25 14:01:31 +08:00 |
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Liphen
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881b1eca3c
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refactor: 删除PC_WID
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2023-12-24 14:13:05 +08:00 |
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Liphen
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a94958d7c9
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refactor: 调整变量名，删除fuNum
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2023-12-24 13:17:55 +08:00 |
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Liphen
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442f51d5a4
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fix(icache): 修复之前icache遗留的问题
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2023-12-23 11:47:35 +08:00 |
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Liphen
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969237a09f
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fix: 修复dcache的size
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2023-12-22 17:57:19 +08:00 |
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Liphen
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c0bdc5a097
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refactor: 部分常量换成XLEN
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2023-12-22 14:28:13 +08:00 |
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Liphen
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76c0f446da
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feat: 增加dcache
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2023-12-22 14:18:32 +08:00 |
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Liphen
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301199c756
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feat: 添加icache成功生成Verilog
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2023-12-21 15:24:57 +08:00 |
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Liphen
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f13b9f009f
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refactor(const): 删除无用信号
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2023-12-19 15:47:11 +08:00 |
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Liphen
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41da1f4c3e
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refactor: 修改info内信号名
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2023-12-19 14:47:40 +08:00 |
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Liphen
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90efc32bca
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feat(csr): 修改misa的ext段
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2023-12-18 16:59:25 +08:00 |
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Liphen
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534e608337
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feat: 修改PC初值
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2023-12-18 15:26:45 +08:00 |
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Liphen
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6f065a9c67
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perf: 缩减op信号，增加bru
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2023-12-13 19:40:01 +08:00 |
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Liphen
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908fd0a377
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增加mmio
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2023-12-13 17:59:38 +08:00 |
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Liphen
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6bd22ee617
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refactor(issue): 美化代码
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2023-12-13 16:31:36 +08:00 |
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Liphen
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6678952dde
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Remove unused code and update variable assignment in Core and Ctrl classes
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2023-12-11 15:20:40 +08:00 |
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Liphen
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452b8ad995
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删除mem_wreg
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2023-12-10 22:23:22 +08:00 |
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Liphen
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2a16d26278
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feat: 通过所有测试用例
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2023-12-07 21:14:40 +08:00 |
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Liphen
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f7ee8c4c87
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成功生成verilog
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2023-12-07 16:08:45 +08:00 |