feat: 添加icache成功生成Verilog
This commit is contained in:
Liphen
parent
f13b9f009f
commit
301199c756
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@ -47,46 +47,46 @@ module top_axi_wrapper(
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);
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PuaCpu core(
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.clock (clock),
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.reset (reset),
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// Interrupts
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.io_ext_int_ei (MEI), // to PLIC
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.io_ext_int_si (MSI), // to CLINT
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.io_ext_int_ti (MTI), // to CLINT
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// aw
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.io_axi_aw_id (MAXI_awid),
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.io_axi_aw_addr (MAXI_awaddr),
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.io_axi_aw_len (MAXI_awlen),
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.io_axi_aw_size (MAXI_awsize),
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.io_axi_aw_burst (MAXI_awburst),
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.io_axi_aw_valid (MAXI_awvalid),
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.io_axi_aw_ready (MAXI_awready),
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// w
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.io_axi_w_data (MAXI_wdata),
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.io_axi_w_strb (MAXI_wstrb),
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.io_axi_w_last (MAXI_wlast),
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.io_axi_w_valid (MAXI_wvalid),
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.io_axi_w_ready (MAXI_wready),
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// b
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.io_axi_b_id (MAXI_bid),
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.io_axi_b_resp (MAXI_bresp),
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.io_axi_b_valid (MAXI_bvalid),
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.io_axi_b_ready (MAXI_bready),
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// ar
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.io_axi_ar_id (MAXI_arid),
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.io_axi_ar_addr (MAXI_araddr),
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.io_axi_ar_len (MAXI_arlen),
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.io_axi_ar_size (MAXI_arsize),
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.io_axi_ar_burst (MAXI_arburst),
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.io_axi_ar_valid (MAXI_arvalid),
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.io_axi_ar_ready (MAXI_arready),
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// r
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.io_axi_r_id (MAXI_rid),
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.io_axi_r_data (MAXI_rdata),
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.io_axi_r_resp (MAXI_rresp),
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.io_axi_r_last (MAXI_rlast),
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.io_axi_r_valid (MAXI_rvalid),
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.io_axi_r_ready (MAXI_rready),
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.clock (clock),
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.reset (reset),
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// Interrupts
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.io_ext_int_ei (MEI), // to PLIC
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.io_ext_int_si (MSI), // to CLINT
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.io_ext_int_ti (MTI), // to CLINT
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// aw
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.io_axi_aw_bits_id (MAXI_awid),
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.io_axi_aw_bits_addr (MAXI_awaddr),
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.io_axi_aw_bits_len (MAXI_awlen),
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.io_axi_aw_bits_size (MAXI_awsize),
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.io_axi_aw_bits_burst (MAXI_awburst),
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.io_axi_aw_valid (MAXI_awvalid),
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.io_axi_aw_ready (MAXI_awready),
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// w
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.io_axi_w_bits_data (MAXI_wdata),
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.io_axi_w_bits_strb (MAXI_wstrb),
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.io_axi_w_bits_last (MAXI_wlast),
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.io_axi_w_valid (MAXI_wvalid),
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.io_axi_w_ready (MAXI_wready),
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// b
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.io_axi_b_bits_id (MAXI_bid),
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.io_axi_b_bits_resp (MAXI_bresp),
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.io_axi_b_valid (MAXI_bvalid),
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.io_axi_b_ready (MAXI_bready),
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// ar
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.io_axi_ar_bits_id (MAXI_arid),
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.io_axi_ar_bits_addr (MAXI_araddr),
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.io_axi_ar_bits_len (MAXI_arlen),
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.io_axi_ar_bits_size (MAXI_arsize),
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.io_axi_ar_bits_burst (MAXI_arburst),
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.io_axi_ar_valid (MAXI_arvalid),
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.io_axi_ar_ready (MAXI_arready),
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// r
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.io_axi_r_bits_id (MAXI_rid),
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.io_axi_r_bits_data (MAXI_rdata),
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.io_axi_r_bits_resp (MAXI_rresp),
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.io_axi_r_bits_last (MAXI_rlast),
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.io_axi_r_valid (MAXI_rvalid),
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.io_axi_r_ready (MAXI_rready),
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// debug
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.io_debug_wb_pc (debug_pc),
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.io_debug_wb_rf_wen (debug_commit),
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@ -15,6 +15,7 @@ import ctrl._
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import mmu._
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import chisel3.util.experimental.decode.decoder
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import cpu.pipeline.fetch.InstFifo
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import cache.mmu.ITlbL1
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class Core(implicit val config: CpuConfig) extends Module {
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val io = IO(new Bundle {
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@ -37,6 +38,10 @@ class Core(implicit val config: CpuConfig) extends Module {
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val memoryUnit = Module(new MemoryUnit()).io
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val writeBackStage = Module(new WriteBackStage()).io
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val writeBackUnit = Module(new WriteBackUnit()).io
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val tlbL1I = Module(new ITlbL1()).io
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tlbL1I.addr := fetchUnit.iCache.pc
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tlbL1I.cache <> io.inst.tlb
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ctrl.decoderUnit <> decoderUnit.ctrl
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ctrl.executeUnit <> executeUnit.ctrl
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@ -4,6 +4,7 @@ import chisel3._
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import chisel3.util._
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import cpu.defines._
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import cpu.CpuConfig
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import cpu.CacheConfig
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class Cache(implicit config: CpuConfig) extends Module {
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val io = IO(new Bundle {
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@ -12,7 +13,9 @@ class Cache(implicit config: CpuConfig) extends Module {
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val axi = new AXI()
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})
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val icache = Module(new ICache())
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implicit val iCacheConfig = CacheConfig(nset = 64, nbank = 4, bankWidth = 16)
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val icache = Module(new ICache(iCacheConfig))
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val dcache = Module(new DCache())
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val axi_interface = Module(new CacheAXIInterface())
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@ -12,32 +12,32 @@ class CacheAXIInterface extends Module {
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})
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// pass-through aw {
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io.axi.aw.id := io.dcache.aw.id
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io.axi.aw.addr := io.dcache.aw.addr
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io.axi.aw.len := io.dcache.aw.len
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io.axi.aw.size := io.dcache.aw.size
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io.axi.aw.burst := io.dcache.aw.burst
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io.axi.aw.valid := io.dcache.aw.valid
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io.axi.aw.prot := io.dcache.aw.prot
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io.axi.aw.cache := io.dcache.aw.cache
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io.axi.aw.lock := io.dcache.aw.lock
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io.dcache.aw.ready := io.axi.aw.ready
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io.axi.aw.bits.id := io.dcache.aw.bits.id
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io.axi.aw.bits.addr := io.dcache.aw.bits.addr
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io.axi.aw.bits.len := io.dcache.aw.bits.len
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io.axi.aw.bits.size := io.dcache.aw.bits.size
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io.axi.aw.bits.burst := io.dcache.aw.bits.burst
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io.axi.aw.valid := io.dcache.aw.valid
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io.axi.aw.bits.prot := io.dcache.aw.bits.prot
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io.axi.aw.bits.cache := io.dcache.aw.bits.cache
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io.axi.aw.bits.lock := io.dcache.aw.bits.lock
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io.dcache.aw.ready := io.axi.aw.ready
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// pass-through aw }
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// pass-through w {
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io.axi.w.id := io.dcache.w.id
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io.axi.w.data := io.dcache.w.data
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io.axi.w.strb := io.dcache.w.strb
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io.axi.w.last := io.dcache.w.last
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io.axi.w.valid := io.dcache.w.valid
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io.dcache.w.ready := io.axi.w.ready
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io.axi.w.bits.id := io.dcache.w.bits.id
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io.axi.w.bits.data := io.dcache.w.bits.data
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io.axi.w.bits.strb := io.dcache.w.bits.strb
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io.axi.w.bits.last := io.dcache.w.bits.last
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io.axi.w.valid := io.dcache.w.valid
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io.dcache.w.ready := io.axi.w.ready
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// pass-through aw }
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// pass-through b {
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io.dcache.b.id := io.axi.b.id
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io.dcache.b.valid := io.axi.b.valid
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io.dcache.b.resp := io.axi.b.resp
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io.axi.b.ready := io.dcache.b.ready
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io.dcache.b.bits.id := io.axi.b.bits.id
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io.dcache.b.valid := io.axi.b.valid
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io.dcache.b.bits.resp := io.axi.b.bits.resp
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io.axi.b.ready := io.dcache.b.ready
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// pass-through b }
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// mux ar {
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@ -55,31 +55,31 @@ class CacheAXIInterface extends Module {
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}
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}
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io.axi.ar.id := Cat(0.U(3.W), ar_sel)
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io.axi.ar.addr := Mux(ar_sel, io.dcache.ar.addr, io.icache.ar.addr)
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io.axi.ar.len := Mux(ar_sel, io.dcache.ar.len, io.icache.ar.len)
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io.axi.ar.size := Mux(ar_sel, io.dcache.ar.size, io.icache.ar.size)
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io.axi.ar.burst := Mux(ar_sel, io.dcache.ar.burst, io.icache.ar.burst)
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io.axi.ar.valid := Mux(ar_sel, io.dcache.ar.valid, io.icache.ar.valid)
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io.axi.ar.prot := Mux(ar_sel, io.dcache.ar.prot, io.icache.ar.prot)
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io.axi.ar.cache := Mux(ar_sel, io.dcache.ar.cache, io.icache.ar.cache)
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io.axi.ar.lock := Mux(ar_sel, io.dcache.ar.lock, io.icache.ar.lock)
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io.icache.ar.ready := !ar_sel && io.axi.ar.ready
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io.dcache.ar.ready := ar_sel && io.axi.ar.ready
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io.axi.ar.bits.id := Cat(0.U(3.W), ar_sel)
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io.axi.ar.bits.addr := Mux(ar_sel, io.dcache.ar.bits.addr, io.icache.ar.bits.addr)
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io.axi.ar.bits.len := Mux(ar_sel, io.dcache.ar.bits.len, io.icache.ar.bits.len)
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io.axi.ar.bits.size := Mux(ar_sel, io.dcache.ar.bits.size, io.icache.ar.bits.size)
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io.axi.ar.bits.burst := Mux(ar_sel, io.dcache.ar.bits.burst, io.icache.ar.bits.burst)
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io.axi.ar.valid := Mux(ar_sel, io.dcache.ar.valid, io.icache.ar.valid)
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io.axi.ar.bits.prot := Mux(ar_sel, io.dcache.ar.bits.prot, io.icache.ar.bits.prot)
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io.axi.ar.bits.cache := Mux(ar_sel, io.dcache.ar.bits.cache, io.icache.ar.bits.cache)
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io.axi.ar.bits.lock := Mux(ar_sel, io.dcache.ar.bits.lock, io.icache.ar.bits.lock)
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io.icache.ar.ready := !ar_sel && io.axi.ar.ready
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io.dcache.ar.ready := ar_sel && io.axi.ar.ready
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// mux ar }
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// mux r based on rid {
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val r_sel = io.axi.r.id(0)
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io.icache.r.id := io.axi.r.id
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io.icache.r.data := io.axi.r.data
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io.icache.r.resp := io.axi.r.resp
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io.icache.r.last := io.axi.r.last
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io.icache.r.valid := !r_sel && io.axi.r.valid
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io.dcache.r.id := io.axi.r.id
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io.dcache.r.data := io.axi.r.data
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io.dcache.r.resp := io.axi.r.resp
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io.dcache.r.last := io.axi.r.last
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io.dcache.r.valid := r_sel && io.axi.r.valid
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io.axi.r.ready := Mux(r_sel, io.dcache.r.ready, io.icache.r.ready)
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val r_sel = io.axi.r.bits.id(0)
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io.icache.r.bits.id := io.axi.r.bits.id
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io.icache.r.bits.data := io.axi.r.bits.data
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io.icache.r.bits.resp := io.axi.r.bits.resp
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io.icache.r.bits.last := io.axi.r.bits.last
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io.icache.r.valid := !r_sel && io.axi.r.valid
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io.dcache.r.bits.id := io.axi.r.bits.id
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io.dcache.r.bits.data := io.axi.r.bits.data
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io.dcache.r.bits.resp := io.axi.r.bits.resp
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io.dcache.r.bits.last := io.axi.r.bits.last
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io.dcache.r.valid := r_sel && io.axi.r.valid
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io.axi.r.ready := Mux(r_sel, io.dcache.r.ready, io.icache.r.ready)
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// mux r based on rid }
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}
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@ -24,39 +24,39 @@ class DCache(implicit config: CpuConfig) extends Module {
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val awvalid = RegInit(false.B)
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val awaddr = RegInit(0.U(AXI_ADDR_WID.W))
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val awsize = RegInit(0.U(AXI_SIZE_WID.W))
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io.axi.aw.id := 1.U
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io.axi.aw.addr := awaddr
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io.axi.aw.len := 0.U
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io.axi.aw.size := awsize
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io.axi.aw.burst := BURST_INCR.U
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io.axi.aw.valid := awvalid
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io.axi.aw.prot := 0.U
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io.axi.aw.lock := 0.U
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io.axi.aw.cache := 0.U
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io.axi.aw.bits.id := 1.U
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io.axi.aw.bits.addr := awaddr
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io.axi.aw.bits.len := 0.U
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io.axi.aw.bits.size := awsize
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io.axi.aw.bits.burst := BURST_INCR.U
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io.axi.aw.valid := awvalid
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io.axi.aw.bits.prot := 0.U
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io.axi.aw.bits.lock := 0.U
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io.axi.aw.bits.cache := 0.U
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val wvalid = RegInit(false.B)
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val wdata = RegInit(0.U(AXI_DATA_WID.W))
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val wstrb = RegInit(0.U(AXI_STRB_WID.W))
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io.axi.w.id := 1.U
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io.axi.w.data := wdata
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io.axi.w.strb := wstrb
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io.axi.w.last := 1.U
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io.axi.w.valid := wvalid
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io.axi.w.bits.id := 1.U
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io.axi.w.bits.data := wdata
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io.axi.w.bits.strb := wstrb
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io.axi.w.bits.last := 1.U
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io.axi.w.valid := wvalid
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io.axi.b.ready := 1.U
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val araddr = RegInit(0.U(AXI_ADDR_WID.W))
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val arsize = RegInit(0.U(AXI_SIZE_WID.W))
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val arvalid = RegInit(false.B)
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io.axi.ar.id := 1.U
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io.axi.ar.addr := araddr
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io.axi.ar.len := 0.U
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io.axi.ar.size := arsize
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io.axi.ar.burst := BURST_INCR.U
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io.axi.ar.valid := arvalid
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io.axi.ar.prot := 0.U
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io.axi.ar.cache := 0.U
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io.axi.ar.lock := 0.U
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io.axi.ar.bits.id := 1.U
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io.axi.ar.bits.addr := araddr
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io.axi.ar.bits.len := 0.U
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io.axi.ar.bits.size := arsize
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io.axi.ar.bits.burst := BURST_INCR.U
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io.axi.ar.valid := arvalid
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io.axi.ar.bits.prot := 0.U
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io.axi.ar.bits.cache := 0.U
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io.axi.ar.bits.lock := 0.U
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val rready = RegInit(false.B)
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io.axi.r.ready := rready
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@ -102,8 +102,8 @@ class DCache(implicit config: CpuConfig) extends Module {
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arvalid := false.B
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}
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when(io.axi.r.valid) {
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saved_rdata := io.axi.r.data
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acc_err := io.axi.r.resp =/= RESP_OKEY.U
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saved_rdata := io.axi.r.bits.data
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acc_err := io.axi.r.bits.resp =/= RESP_OKEY.U
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status := s_idle
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}
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}
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@ -115,7 +115,7 @@ class DCache(implicit config: CpuConfig) extends Module {
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wvalid := false.B
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}
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when(io.axi.b.valid) {
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acc_err := io.axi.b.resp =/= RESP_OKEY.U
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acc_err := io.axi.b.bits.resp =/= RESP_OKEY.U
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status := s_idle
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}
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}
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@ -1,70 +1,201 @@
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// * Cache 设计借鉴了nscscc2021 cqu的cdim * //
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package cache
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import chisel3._
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import chisel3.util._
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import memory._
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import cpu.CacheConfig
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import cpu.defines._
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import cpu.CpuConfig
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import cpu.defines.Const._
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class ICache(implicit config: CpuConfig) extends Module {
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class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Module {
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val nway: Int = cacheConfig.nway
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val nset: Int = cacheConfig.nset
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val nbank: Int = cacheConfig.nbank
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val ninst: Int = cacheConfig.ninst // 取指令的数量
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val bankOffsetWidth: Int = cacheConfig.bankOffsetWidth
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val bankWidth: Int = cacheConfig.bankWidth
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val tagWidth: Int = cacheConfig.tagWidth
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val indexWidth: Int = cacheConfig.indexWidth
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val offsetWidth: Int = cacheConfig.offsetWidth
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val io = IO(new Bundle {
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val cpu = Flipped(new Cache_ICache())
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val axi = new ICache_AXIInterface()
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})
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require(isPow2(ninst), "ninst must be power of 2")
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// * addr organization * //
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// ======================================
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// | tag | index |offset|
|
||||
// |31 12|11 6|5 0|
|
||||
// ======================================
|
||||
// | offset |
|
||||
// | bank index | bank offset |
|
||||
// | 5 4 | 3 2 |
|
||||
// ============================
|
||||
|
||||
val tlb_fill = RegInit(false.B)
|
||||
// * fsm * //
|
||||
val s_idle :: s_uncached :: s_replace :: s_save :: Nil = Enum(4)
|
||||
val status = RegInit(s_idle)
|
||||
val state = RegInit(s_idle)
|
||||
|
||||
val read_next_addr = (status === s_idle || status === s_save)
|
||||
val pc = Cat(io.cpu.addr(read_next_addr)(31, 2), 0.U(2.W))
|
||||
// * nway * nset * //
|
||||
// * 128 bit for 4 inst * //
|
||||
// =========================================================
|
||||
// | valid | tag | bank 0 | bank 1 | bank 2 | bank 3 |
|
||||
// | 1 | 20 | 128 | 128 | 128 | 128 |
|
||||
// =========================================================
|
||||
// | bank |
|
||||
// | inst 0 | inst 1 | inst 2 | inst 3 |
|
||||
// | 32 | 32 | 32 | 32 |
|
||||
// =====================================
|
||||
val instperbank = bankWidth / 4 // 每个bank存储的指令数
|
||||
val valid = RegInit(VecInit(Seq.fill(nset * nbank)(VecInit(Seq.fill(instperbank)(false.B)))))
|
||||
|
||||
// default
|
||||
val arvalid = RegInit(false.B)
|
||||
val araddr = RegInit(0.U(AXI_ADDR_WID.W))
|
||||
io.axi.ar.id := 0.U
|
||||
io.axi.ar.addr := araddr
|
||||
io.axi.ar.len := 0.U
|
||||
io.axi.ar.size := 2.U
|
||||
io.axi.ar.lock := 0.U
|
||||
io.axi.ar.burst := BURST_INCR.U
|
||||
io.axi.ar.valid := arvalid
|
||||
io.axi.ar.prot := 0.U
|
||||
io.axi.ar.cache := 0.U
|
||||
val data = Wire(Vec(nway, Vec(instperbank, UInt(DATA_WID.W))))
|
||||
val tag = RegInit(VecInit(Seq.fill(nway)(0.U(tagWidth.W))))
|
||||
|
||||
val rready = RegInit(false.B)
|
||||
val saved = RegInit(VecInit(Seq.fill(config.instFetchNum)(0.U.asTypeOf(new Bundle {
|
||||
val inst = UInt(AXI_DATA_WID.W)
|
||||
// * should choose next addr * //
|
||||
val should_next_addr = (state === s_idle && !tlb_fill) || (state === s_save)
|
||||
|
||||
val data_raddr = io.cpu.addr(should_next_addr)(indexWidth + offsetWidth - 1, bankOffsetWidth)
|
||||
val data_wstrb = RegInit(VecInit(Seq.fill(nway)(VecInit(Seq.fill(instperbank)(0.U(4.W))))))
|
||||
|
||||
val tag_raddr = io.cpu.addr(should_next_addr)(indexWidth + offsetWidth - 1, offsetWidth)
|
||||
val tag_wstrb = RegInit(VecInit(Seq.fill(nway)(false.B)))
|
||||
val tag_wdata = RegInit(0.U(tagWidth.W))
|
||||
|
||||
// * lru * //
|
||||
val lru = RegInit(VecInit(Seq.fill(nset * nbank)(false.B)))
|
||||
|
||||
// * itlb * //
|
||||
when(tlb_fill) { tlb_fill := false.B }
|
||||
io.cpu.tlb.fill := tlb_fill
|
||||
io.cpu.tlb.icache_is_save := (state === s_save)
|
||||
|
||||
// * fence * //
|
||||
when(io.cpu.fence && !io.cpu.icache_stall && io.cpu.cpu_ready) {
|
||||
valid.map(_ := VecInit(Seq.fill(instperbank)(false.B)))
|
||||
}
|
||||
|
||||
// * replace set * //
|
||||
val rset = RegInit(0.U(6.W))
|
||||
|
||||
// * virtual set * //
|
||||
val vset = io.cpu.addr(0)(indexWidth + offsetWidth - 1, offsetWidth)
|
||||
|
||||
// * cache hit * //
|
||||
val tag_compare_valid = VecInit(Seq.tabulate(nway)(i => tag(i) === io.cpu.tlb.tag && valid(vset)(i)))
|
||||
val cache_hit = tag_compare_valid.contains(true.B)
|
||||
val cache_hit_available = cache_hit && io.cpu.tlb.translation_ok && !io.cpu.tlb.uncached
|
||||
val sel = tag_compare_valid(1)
|
||||
|
||||
val bank_offset = io.cpu.addr(0)(log2Ceil(instperbank) + 1, 2)
|
||||
val inst = VecInit(
|
||||
Seq.tabulate(instperbank)(i => Mux(i.U <= (3.U - bank_offset), data(sel)(i.U + bank_offset), 0.U))
|
||||
)
|
||||
val inst_valid = VecInit(Seq.tabulate(instperbank)(i => cache_hit_available && i.U <= (3.U - bank_offset)))
|
||||
|
||||
val saved = RegInit(VecInit(Seq.fill(instperbank)(0.U.asTypeOf(new Bundle {
|
||||
val inst = UInt(PC_WID.W)
|
||||
val valid = Bool()
|
||||
}))))
|
||||
io.axi.r.ready := true.B
|
||||
|
||||
val axi_cnt = Counter(cacheConfig.burstSize)
|
||||
|
||||
// bank tag ram
|
||||
for { i <- 0 until nway; j <- 0 until instperbank } {
|
||||
val bank = Module(new SimpleDualPortRam(nset * nbank, INST_BANK_WID, byteAddressable = true))
|
||||
bank.io.ren := true.B
|
||||
bank.io.raddr := data_raddr
|
||||
data(i)(j) := bank.io.rdata
|
||||
|
||||
bank.io.wen := data_wstrb(i)(j).orR
|
||||
bank.io.waddr := Cat(rset, axi_cnt.value(log2Ceil(cacheConfig.burstSize) - 1, log2Ceil(instperbank)))
|
||||
bank.io.wdata := Mux(
|
||||
j.U === axi_cnt.value(log2Ceil(instperbank) - 1, 0),
|
||||
Mux(axi_cnt.value(0) === 0.U, io.axi.r.bits.data(31, 0), io.axi.r.bits.data(63, 32)),
|
||||
0.U
|
||||
)
|
||||
bank.io.wstrb := data_wstrb(i)(j)
|
||||
}
|
||||
|
||||
for { i <- 0 until ninst } {
|
||||
io.cpu.inst_valid(i) := Mux(state === s_idle && !tlb_fill, inst_valid(i), saved(i).valid) && io.cpu.req
|
||||
io.cpu.inst(i) := Mux(state === s_idle && !tlb_fill, inst(i), saved(i).inst)
|
||||
}
|
||||
|
||||
for { i <- 0 until nway } {
|
||||
val tag_bram = Module(new LUTRam(nset, tagWidth))
|
||||
tag_bram.io.raddr := tag_raddr
|
||||
tag(i) := tag_bram.io.rdata
|
||||
|
||||
tag_bram.io.wen := tag_wstrb(i)
|
||||
tag_bram.io.waddr := rset
|
||||
tag_bram.io.wdata := tag_wdata
|
||||
}
|
||||
|
||||
io.cpu.icache_stall := Mux(state === s_idle && !tlb_fill, (!cache_hit_available && io.cpu.req), state =/= s_save)
|
||||
|
||||
val ar_init = WireInit(0.U.asTypeOf(new AR()))
|
||||
ar_init.burst := 1.U
|
||||
val ar = RegInit(ar_init)
|
||||
val arvalid = RegInit(false.B)
|
||||
ar <> io.axi.ar.bits
|
||||
arvalid <> io.axi.ar.valid
|
||||
|
||||
val r = RegInit(0.U.asTypeOf(new R()))
|
||||
val rready = RegInit(false.B)
|
||||
r <> io.axi.r.bits
|
||||
rready <> io.axi.r.ready
|
||||
|
||||
val acc_err = RegInit(false.B)
|
||||
val addr_err = io.cpu.addr(read_next_addr)(63, 32).orR
|
||||
val addr_err = io.cpu.addr(should_next_addr)(XLEN - 1, PADDR_WID).orR
|
||||
|
||||
(0 until config.instFetchNum).foreach(i => {
|
||||
io.cpu.inst(i) := Mux(status === s_idle && !acc_err, 0.U, saved(i).inst)
|
||||
io.cpu.inst_valid(i) := Mux(status === s_idle && !acc_err, false.B, saved(i).valid) && io.cpu.req
|
||||
})
|
||||
when(acc_err) { acc_err := false.B }
|
||||
io.cpu.acc_err := acc_err
|
||||
|
||||
io.cpu.acc_err := acc_err
|
||||
io.cpu.icache_stall := Mux(status === s_idle && !acc_err, io.cpu.req, status =/= s_save)
|
||||
|
||||
switch(status) {
|
||||
switch(state) {
|
||||
is(s_idle) {
|
||||
acc_err := false.B
|
||||
when(io.cpu.req) {
|
||||
when(tlb_fill) {
|
||||
when(!io.cpu.tlb.hit) {
|
||||
state := s_save
|
||||
saved(0).inst := 0.U
|
||||
saved(0).valid := true.B
|
||||
}
|
||||
}.elsewhen(io.cpu.req) {
|
||||
when(addr_err) {
|
||||
acc_err := true.B
|
||||
state := s_save
|
||||
saved(0).inst := 0.U
|
||||
saved(0).valid := true.B
|
||||
status := s_save
|
||||
}.otherwise {
|
||||
araddr := pc
|
||||
arvalid := true.B
|
||||
io.axi.ar.len := 0.U
|
||||
io.axi.ar.size := 2.U
|
||||
status := s_uncached
|
||||
}.elsewhen(!io.cpu.tlb.translation_ok) {
|
||||
tlb_fill := true.B
|
||||
}.elsewhen(io.cpu.tlb.uncached) {
|
||||
state := s_uncached
|
||||
ar.addr := io.cpu.tlb.pa
|
||||
ar.len := 0.U(log2Ceil((nbank * bankWidth) / 4).W)
|
||||
ar.size := 2.U(bankOffsetWidth.W)
|
||||
arvalid := true.B
|
||||
}.elsewhen(!cache_hit) {
|
||||
state := s_replace
|
||||
ar.addr := Cat(io.cpu.tlb.pa(31, 6), 0.U(6.W))
|
||||
ar.len := 15.U(log2Ceil((nbank * bankWidth) / 4).W)
|
||||
ar.size := 2.U(bankOffsetWidth.W)
|
||||
arvalid := true.B
|
||||
|
||||
rset := vset
|
||||
(0 until instperbank).foreach(i => data_wstrb(lru(vset))(i) := Mux(i.U === 0.U, 0xf.U, 0x0.U))
|
||||
tag_wstrb(lru(vset)) := true.B
|
||||
tag_wdata := io.cpu.tlb.tag
|
||||
valid(vset)(lru(vset)) := true.B
|
||||
axi_cnt.reset()
|
||||
}.elsewhen(!io.cpu.icache_stall) {
|
||||
lru(vset) := ~sel
|
||||
when(!io.cpu.cpu_ready) {
|
||||
state := s_save
|
||||
(1 until instperbank).foreach(i => saved(i).inst := data(sel)(i))
|
||||
(0 until instperbank).foreach(i => saved(i).valid := inst_valid(i))
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -74,18 +205,40 @@ class ICache(implicit config: CpuConfig) extends Module {
|
|||
arvalid := false.B
|
||||
rready := true.B
|
||||
}
|
||||
}.elsewhen(io.axi.r.valid && io.axi.r.ready) {
|
||||
saved(0).inst := Mux(araddr(2), io.axi.r.data(63, 32), io.axi.r.data(31, 0))
|
||||
}.elsewhen(io.axi.r.fire) {
|
||||
// * uncached not support burst transport * //
|
||||
state := s_save
|
||||
saved(0).inst := io.axi.r.bits.data
|
||||
saved(0).valid := true.B
|
||||
acc_err := io.axi.r.resp =/= RESP_OKEY.U
|
||||
rready := false.B
|
||||
status := s_save
|
||||
acc_err := io.axi.r.bits.resp =/= RESP_OKEY.U
|
||||
}
|
||||
}
|
||||
is(s_replace) {
|
||||
when(io.axi.ar.valid) {
|
||||
when(io.axi.ar.ready) {
|
||||
arvalid := false.B
|
||||
rready := true.B
|
||||
}
|
||||
}.elsewhen(io.axi.r.fire) {
|
||||
// * burst transport * //
|
||||
when(!io.axi.r.bits.last) {
|
||||
axi_cnt.inc()
|
||||
data_wstrb(lru(vset))(0) := data_wstrb(lru(vset))(instperbank - 1)
|
||||
(1 until instperbank).foreach(i => data_wstrb(lru(vset))(i) := data_wstrb(lru(vset))(i - 1))
|
||||
}.otherwise {
|
||||
rready := false.B
|
||||
data_wstrb(lru(vset)) := 0.U.asTypeOf(Vec(instperbank, UInt(4.W)))
|
||||
tag_wstrb(lru(vset)) := false.B
|
||||
}
|
||||
}.elsewhen(!io.axi.r.ready) {
|
||||
state := s_idle
|
||||
}
|
||||
}
|
||||
is(s_save) {
|
||||
when(io.cpu.cpu_ready && !io.cpu.icache_stall) {
|
||||
status := s_idle
|
||||
(0 until config.instFetchNum).foreach(i => saved(i).valid := false.B)
|
||||
state := s_idle
|
||||
(0 until instperbank).foreach(i => saved(i).valid := false.B)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,21 @@
|
|||
package cache.mmu
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import cpu.defines._
|
||||
import cpu.defines.Const._
|
||||
|
||||
class ITlbL1 extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val addr = Input(UInt(PC_WID.W))
|
||||
val cache = new Tlb_ICache()
|
||||
})
|
||||
val vpn = io.addr(31, 12)
|
||||
val direct_mapped = io.addr(31, 30) === 2.U(2.W)
|
||||
|
||||
io.cache.uncached := AddressSpace.isMMIO(io.addr)
|
||||
io.cache.translation_ok := true.B
|
||||
io.cache.hit := true.B
|
||||
io.cache.tag := io.addr(31, 12)
|
||||
io.cache.pa := Cat(io.cache.tag, io.addr(11, 0))
|
||||
}
|
||||
|
|
@ -113,6 +113,9 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
|
|||
val inst_valid = Input(Vec(config.instFetchNum, Bool()))
|
||||
val acc_err = Input(Bool())
|
||||
val icache_stall = Input(Bool()) // icache_stall
|
||||
|
||||
// tlb
|
||||
val tlb = new Tlb_ICache()
|
||||
}
|
||||
|
||||
// cpu to dcache
|
||||
|
|
@ -135,72 +138,55 @@ class Cache_DCache extends Bundle {
|
|||
// master -> slave
|
||||
|
||||
class AR extends Bundle {
|
||||
val id = Output(UInt(AXI_ID_WID.W))
|
||||
val addr = Output(UInt(AXI_ADDR_WID.W))
|
||||
val len = Output(UInt(AXI_LEN_WID.W))
|
||||
val size = Output(UInt(AXI_SIZE_WID.W))
|
||||
val burst = Output(UInt(AXI_BURST_WID.W))
|
||||
val lock = Output(UInt(AXI_LOCK_WID.W))
|
||||
val cache = Output(UInt(AXI_CACHE_WID.W))
|
||||
val prot = Output(UInt(AXI_PROT_WID.W))
|
||||
val valid = Output(Bool())
|
||||
|
||||
val ready = Input(Bool())
|
||||
val id = UInt(AXI_ID_WID.W)
|
||||
val addr = UInt(AXI_ADDR_WID.W)
|
||||
val len = UInt(AXI_LEN_WID.W)
|
||||
val size = UInt(AXI_SIZE_WID.W)
|
||||
val burst = UInt(AXI_BURST_WID.W)
|
||||
val lock = UInt(AXI_LOCK_WID.W)
|
||||
val cache = UInt(AXI_CACHE_WID.W)
|
||||
val prot = UInt(AXI_PROT_WID.W)
|
||||
}
|
||||
|
||||
class R extends Bundle {
|
||||
val ready = Output(Bool())
|
||||
|
||||
val id = Input(UInt(AXI_ID_WID.W))
|
||||
val data = Input(UInt(AXI_DATA_WID.W))
|
||||
val resp = Input(UInt(AXI_RESP_WID.W))
|
||||
val last = Input(Bool())
|
||||
val valid = Input(Bool())
|
||||
val id = UInt(AXI_ID_WID.W)
|
||||
val data = UInt(AXI_DATA_WID.W)
|
||||
val resp = UInt(AXI_RESP_WID.W)
|
||||
val last = Bool()
|
||||
}
|
||||
|
||||
class AW extends Bundle {
|
||||
val id = Output(UInt(AXI_ID_WID.W))
|
||||
val addr = Output(UInt(AXI_ADDR_WID.W))
|
||||
val len = Output(UInt(AXI_LEN_WID.W))
|
||||
val size = Output(UInt(AXI_SIZE_WID.W))
|
||||
val burst = Output(UInt(AXI_BURST_WID.W))
|
||||
val lock = Output(UInt(AXI_LOCK_WID.W))
|
||||
val cache = Output(UInt(AXI_CACHE_WID.W))
|
||||
val prot = Output(UInt(AXI_PROT_WID.W))
|
||||
val valid = Output(Bool())
|
||||
|
||||
val ready = Input(Bool())
|
||||
val id = UInt(AXI_ID_WID.W)
|
||||
val addr = UInt(AXI_ADDR_WID.W)
|
||||
val len = UInt(AXI_LEN_WID.W)
|
||||
val size = UInt(AXI_SIZE_WID.W)
|
||||
val burst = UInt(AXI_BURST_WID.W)
|
||||
val lock = UInt(AXI_LOCK_WID.W)
|
||||
val cache = UInt(AXI_CACHE_WID.W)
|
||||
val prot = UInt(AXI_PROT_WID.W)
|
||||
}
|
||||
|
||||
class W extends Bundle {
|
||||
val id = Output(UInt(AXI_ID_WID.W))
|
||||
val data = Output(UInt(AXI_DATA_WID.W))
|
||||
val strb = Output(UInt(AXI_STRB_WID.W))
|
||||
val last = Output(Bool())
|
||||
val valid = Output(Bool())
|
||||
|
||||
val ready = Input(Bool())
|
||||
val id = UInt(AXI_ID_WID.W)
|
||||
val data = UInt(AXI_DATA_WID.W)
|
||||
val strb = UInt(AXI_STRB_WID.W)
|
||||
val last = Bool()
|
||||
}
|
||||
|
||||
class B extends Bundle {
|
||||
val ready = Output(Bool())
|
||||
|
||||
val id = Input(UInt(AXI_ID_WID.W))
|
||||
val resp = Input(UInt(AXI_RESP_WID.W))
|
||||
val valid = Input(Bool())
|
||||
val id = UInt(AXI_ID_WID.W)
|
||||
val resp = UInt(AXI_RESP_WID.W)
|
||||
}
|
||||
|
||||
class ICache_AXIInterface extends Bundle {
|
||||
val ar = new AR()
|
||||
val r = new R()
|
||||
val ar = Decoupled(new AR())
|
||||
val r = Flipped(Decoupled(new R()))
|
||||
}
|
||||
|
||||
class DCache_AXIInterface extends Bundle {
|
||||
val aw = new AW()
|
||||
val w = new W()
|
||||
val b = new B()
|
||||
val ar = new AR()
|
||||
val r = new R()
|
||||
class DCache_AXIInterface extends ICache_AXIInterface {
|
||||
val aw = Decoupled(new AW())
|
||||
val w = Decoupled(new W())
|
||||
val b = Flipped(Decoupled(new B()))
|
||||
}
|
||||
|
||||
class Cache_AXIInterface extends Bundle {
|
||||
|
|
@ -211,11 +197,11 @@ class Cache_AXIInterface extends Bundle {
|
|||
|
||||
// AXI interface
|
||||
class AXI extends Bundle {
|
||||
val ar = new AR() // read address channel
|
||||
val r = new R() // read data channel
|
||||
val aw = new AW() // write address channel
|
||||
val w = new W() // write data channel
|
||||
val b = new B() // write response channel
|
||||
val ar = Decoupled(new AR()) // read address channel
|
||||
val r = Flipped(Decoupled(new R())) // read data channel
|
||||
val aw = Decoupled(new AW()) // write address channel
|
||||
val w = Decoupled(new W()) // write data channel
|
||||
val b = Flipped(Decoupled(new B())) // write response channel
|
||||
}
|
||||
|
||||
class DEBUG extends Bundle {
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ trait Constants extends CoreParameter {
|
|||
val EXC_WID = 16
|
||||
|
||||
// inst rom
|
||||
val INST_BANK_WID = 32
|
||||
val INST_WID = XLEN
|
||||
val INST_ADDR_WID = XLEN
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,124 @@
|
|||
package cpu.defines
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
sealed trait Sv39Const extends CoreParameter {
|
||||
val PAddrBits = PADDR_WID
|
||||
val Level = 3
|
||||
val offLen = 12
|
||||
val ppn0Len = 9
|
||||
val ppn1Len = 9
|
||||
val ppn2Len = PAddrBits - offLen - ppn0Len - ppn1Len // 2
|
||||
val ppnLen = ppn2Len + ppn1Len + ppn0Len
|
||||
val vpn2Len = 9
|
||||
val vpn1Len = 9
|
||||
val vpn0Len = 9
|
||||
val vpnLen = vpn2Len + vpn1Len + vpn0Len
|
||||
|
||||
//val paddrLen = PAddrBits
|
||||
//val vaddrLen = VAddrBits
|
||||
val satpLen = XLEN
|
||||
val satpModeLen = 4
|
||||
val asidLen = 16
|
||||
val flagLen = 8
|
||||
|
||||
val ptEntryLen = XLEN
|
||||
val satpResLen = XLEN - ppnLen - satpModeLen - asidLen
|
||||
//val vaResLen = 25 // unused
|
||||
//val paResLen = 25 // unused
|
||||
val pteResLen = XLEN - ppnLen - 2 - flagLen
|
||||
|
||||
def vaBundle = new Bundle {
|
||||
val vpn2 = UInt(vpn2Len.W)
|
||||
val vpn1 = UInt(vpn1Len.W)
|
||||
val vpn0 = UInt(vpn0Len.W)
|
||||
val off = UInt(offLen.W)
|
||||
}
|
||||
|
||||
def vaBundle2 = new Bundle {
|
||||
val vpn = UInt(vpnLen.W)
|
||||
val off = UInt(offLen.W)
|
||||
}
|
||||
|
||||
def vaBundle3 = new Bundle {
|
||||
val vpn = UInt(vpnLen.W)
|
||||
val off = UInt(offLen.W)
|
||||
}
|
||||
|
||||
def vpnBundle = new Bundle {
|
||||
val vpn2 = UInt(vpn2Len.W)
|
||||
val vpn1 = UInt(vpn1Len.W)
|
||||
val vpn0 = UInt(vpn0Len.W)
|
||||
}
|
||||
|
||||
def paBundle = new Bundle {
|
||||
val ppn2 = UInt(ppn2Len.W)
|
||||
val ppn1 = UInt(ppn1Len.W)
|
||||
val ppn0 = UInt(ppn0Len.W)
|
||||
val off = UInt(offLen.W)
|
||||
}
|
||||
|
||||
def paBundle2 = new Bundle {
|
||||
val ppn = UInt(ppnLen.W)
|
||||
val off = UInt(offLen.W)
|
||||
}
|
||||
|
||||
def paddrApply(ppn: UInt, vpnn: UInt): UInt = {
|
||||
Cat(Cat(ppn, vpnn), 0.U(3.W))
|
||||
}
|
||||
|
||||
def pteBundle = new Bundle {
|
||||
val reserved = UInt(pteResLen.W)
|
||||
val ppn = UInt(ppnLen.W)
|
||||
val rsw = UInt(2.W)
|
||||
val flag = new Bundle {
|
||||
val d = UInt(1.W)
|
||||
val a = UInt(1.W)
|
||||
val g = UInt(1.W)
|
||||
val u = UInt(1.W)
|
||||
val x = UInt(1.W)
|
||||
val w = UInt(1.W)
|
||||
val r = UInt(1.W)
|
||||
val v = UInt(1.W)
|
||||
}
|
||||
}
|
||||
|
||||
def satpBundle = new Bundle {
|
||||
val mode = UInt(satpModeLen.W)
|
||||
val asid = UInt(asidLen.W)
|
||||
val res = UInt(satpResLen.W)
|
||||
val ppn = UInt(ppnLen.W)
|
||||
}
|
||||
|
||||
def flagBundle = new Bundle {
|
||||
val d = Bool()
|
||||
val a = Bool()
|
||||
val g = Bool()
|
||||
val u = Bool()
|
||||
val x = Bool()
|
||||
val w = Bool()
|
||||
val r = Bool()
|
||||
val v = Bool()
|
||||
}
|
||||
|
||||
def maskPaddr(ppn: UInt, vaddr: UInt, mask: UInt) = {
|
||||
MaskData(vaddr, Cat(ppn, 0.U(offLen.W)), Cat(Fill(ppn2Len, 1.U(1.W)), mask, 0.U(offLen.W)))
|
||||
}
|
||||
|
||||
def MaskEQ(mask: UInt, pattern: UInt, vpn: UInt) = {
|
||||
(Cat("h1ff".U(vpn2Len.W), mask) & pattern) === (Cat("h1ff".U(vpn2Len.W), mask) & vpn)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
class Tlb_ICache extends Bundle {
|
||||
val fill = Input(Bool())
|
||||
val icache_is_save = Input(Bool())
|
||||
val uncached = Output(Bool())
|
||||
|
||||
val translation_ok = Output(Bool())
|
||||
val hit = Output(Bool())
|
||||
val tag = Output(UInt(20.W))
|
||||
val pa = Output(UInt(32.W))
|
||||
}
|
||||
Loading…
Reference in New Issue