Remove unused code and update variable assignment in Core and Ctrl classes
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cface2454d
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@ -38,7 +38,6 @@ class Core(implicit val config: CpuConfig) extends Module {
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val writeBackStage = Module(new WriteBackStage()).io
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val writeBackUnit = Module(new WriteBackUnit()).io
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ctrl.instFifo.has2insts := !(instFifo.empty || instFifo.almost_empty)
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ctrl.decoderUnit <> decoderUnit.ctrl
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ctrl.executeUnit <> executeUnit.ctrl
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ctrl.memoryUnit <> memoryUnit.ctrl
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@ -103,7 +102,7 @@ class Core(implicit val config: CpuConfig) extends Module {
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memoryUnit.csr <> csr.memoryUnit
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memoryUnit.writeBackStage <> writeBackStage.memoryUnit
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csr.ext_int := io.ext_int
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csr.ext_int := io.ext_int
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memoryUnit.dataMemory.in.rdata := io.data.rdata
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memoryUnit.dataMemory.in.acc_err := io.data.acc_err
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@ -10,7 +10,6 @@ class Ctrl(implicit val config: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val cacheCtrl = Flipped(new CacheCtrl())
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val fetchUnit = Flipped(new FetchUnitCtrl())
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val instFifo = Flipped(new InstFifoCtrl())
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val decoderUnit = Flipped(new DecoderUnitCtrl())
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val executeUnit = Flipped(new ExecuteCtrl())
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val memoryUnit = Flipped(new MemoryCtrl())
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@ -61,10 +61,6 @@ class FetchUnitCtrl extends Bundle {
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val do_flush = Input(Bool())
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}
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class InstFifoCtrl extends Bundle {
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val has2insts = Output(Bool())
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}
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class DecoderUnitCtrl extends Bundle {
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val inst0 = Output(new Bundle {
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val src1 = new SrcReadSignal()
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@ -51,10 +51,6 @@ class CsrDecoderUnit extends Bundle {
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class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
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val io = IO(new Bundle {
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val ext_int = Input(new ExtInterrupt())
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val ctrl = Input(new Bundle {
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val exe_stall = Bool()
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val mem_stall = Bool()
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})
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val decoderUnit = new CsrDecoderUnit()
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val executeUnit = new CsrExecuteUnit()
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val memoryUnit = new CsrMemoryUnit()
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