diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala
index f2d0b16..8f2480f 100644
--- a/chisel/playground/src/Core.scala
+++ b/chisel/playground/src/Core.scala
@@ -38,7 +38,6 @@ class Core(implicit val config: CpuConfig) extends Module {
   val writeBackStage = Module(new WriteBackStage()).io
   val writeBackUnit  = Module(new WriteBackUnit()).io
 
-  ctrl.instFifo.has2insts := !(instFifo.empty || instFifo.almost_empty)
   ctrl.decoderUnit <> decoderUnit.ctrl
   ctrl.executeUnit <> executeUnit.ctrl
   ctrl.memoryUnit <> memoryUnit.ctrl
@@ -103,7 +102,7 @@ class Core(implicit val config: CpuConfig) extends Module {
   memoryUnit.csr <> csr.memoryUnit
   memoryUnit.writeBackStage <> writeBackStage.memoryUnit
 
-  csr.ext_int        := io.ext_int
+  csr.ext_int := io.ext_int
 
   memoryUnit.dataMemory.in.rdata   := io.data.rdata
   memoryUnit.dataMemory.in.acc_err := io.data.acc_err
diff --git a/chisel/playground/src/ctrl/Ctrl.scala b/chisel/playground/src/ctrl/Ctrl.scala
index 3c1b0cd..ed83087 100644
--- a/chisel/playground/src/ctrl/Ctrl.scala
+++ b/chisel/playground/src/ctrl/Ctrl.scala
@@ -10,7 +10,6 @@ class Ctrl(implicit val config: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val cacheCtrl     = Flipped(new CacheCtrl())
     val fetchUnit     = Flipped(new FetchUnitCtrl())
-    val instFifo      = Flipped(new InstFifoCtrl())
     val decoderUnit   = Flipped(new DecoderUnitCtrl())
     val executeUnit   = Flipped(new ExecuteCtrl())
     val memoryUnit    = Flipped(new MemoryCtrl())
diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala
index 986f68f..9b52e47 100644
--- a/chisel/playground/src/defines/Bundles.scala
+++ b/chisel/playground/src/defines/Bundles.scala
@@ -61,10 +61,6 @@ class FetchUnitCtrl extends Bundle {
   val do_flush    = Input(Bool())
 }
 
-class InstFifoCtrl extends Bundle {
-  val has2insts = Output(Bool())
-}
-
 class DecoderUnitCtrl extends Bundle {
   val inst0 = Output(new Bundle {
     val src1 = new SrcReadSignal()
diff --git a/chisel/playground/src/pipeline/execute/Csr.scala b/chisel/playground/src/pipeline/execute/Csr.scala
index 3e43165..c7d8745 100644
--- a/chisel/playground/src/pipeline/execute/Csr.scala
+++ b/chisel/playground/src/pipeline/execute/Csr.scala
@@ -51,10 +51,6 @@ class CsrDecoderUnit extends Bundle {
 class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
   val io = IO(new Bundle {
     val ext_int = Input(new ExtInterrupt())
-    val ctrl = Input(new Bundle {
-      val exe_stall = Bool()
-      val mem_stall = Bool()
-    })
     val decoderUnit = new CsrDecoderUnit()
     val executeUnit = new CsrExecuteUnit()
     val memoryUnit  = new CsrMemoryUnit()