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fix: 修复dcache的size

This commit is contained in:
Liphen 2023-12-22 17:57:19 +08:00
parent faa9fca6b9
commit 969237a09f
4 changed files with 26 additions and 28 deletions
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14
chisel/playground/src/CpuConfig.scala
View File

@ -34,13 +34,13 @@ case class CacheConfig(
bankWidth: Int // bytes per bank
) {
val config = CpuConfig()
val indexWidth = log2Ceil(nset) // 6
val bankIndexWidth = log2Ceil(nbank) // 3
val bankOffsetWidth = log2Ceil(bankWidth) // 3
val offsetWidth = bankIndexWidth + bankOffsetWidth // 6
val tagWidth = 32 - indexWidth - offsetWidth // 20
val tagvWidth = tagWidth + 1 // 21
val bankWidthBits = bankWidth * 8 // 64
val indexWidth = log2Ceil(nset)
val bankIndexWidth = log2Ceil(nbank)
val bankOffsetWidth = log2Ceil(bankWidth)
val offsetWidth = bankIndexWidth + bankOffsetWidth
val tagWidth = 32 - indexWidth - offsetWidth
val tagvWidth = tagWidth + 1
val bankWidthBits = bankWidth * 8
val burstSize = 16
val ninst = config.instFetchNum // TODO:改成可随意修改的参数
require(isPow2(nset))

7
chisel/playground/src/cache/Cache.scala vendored
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@ -3,6 +3,7 @@ package cache
import chisel3._
import chisel3.util._
import cpu.defines._
import cpu.defines.Const._
import cpu.CpuConfig
import cpu.CacheConfig
@ -13,8 +14,10 @@ class Cache(implicit config: CpuConfig) extends Module {
val axi = new AXI()
})
implicit val iCacheConfig = CacheConfig(nset = 64, nbank = 4, bankWidth = 16)
implicit val dCacheConfig = CacheConfig(nset = 128, bankWidth = 4)
implicit val iCacheConfig =
CacheConfig(nset = 64, nbank = 4, bankWidth = (32 / 8) * 4) // 每个 bank 存 4 条 32 bit 指令
implicit val dCacheConfig =
CacheConfig(nset = 128, bankWidth = XLEN / 8) // 每个 bank 存 1 条 XLEN bit 数据
val icache = Module(new ICache(iCacheConfig))
val dcache = Module(new DCache(dCacheConfig))

31
chisel/playground/src/cache/DCache.scala vendored
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@ -11,8 +11,8 @@ import cpu.defines.Const._
class WriteBufferUnit extends Bundle {
val data = UInt(XLEN.W)
val addr = UInt(DATA_ADDR_WID.W)
val strb = UInt(4.W)
val size = UInt(2.W)
val strb = UInt(AXI_STRB_WID.W)
val size = UInt(AXI_SIZE_WID.W)
}
class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Module {
@ -56,7 +56,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
val valid = Bool()
val set = UInt(6.W)
val waddr = UInt(10.W)
val wstrb = Vec(nway, UInt(4.W))
val wstrb = Vec(nway, UInt(AXI_STRB_WID.W))
val working = Bool()
val writeback = Bool()
}))
@ -73,7 +73,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
val aw_handshake = RegInit(false.B)
val data_raddr = Mux(victim.valid, victim_addr, io.cpu.addr(11, 2))
val data_wstrb = Wire(Vec(nway, UInt(4.W)))
val data_wstrb = Wire(Vec(nway, UInt(AXI_STRB_WID.W)))
val data_waddr = Mux(victim.valid, victim.waddr, io.cpu.addr(11, 2))
val data_wdata = Mux(state === s_replace, io.axi.r.bits.data, io.cpu.wdata)
@ -142,16 +142,11 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
data_wstrb(i) := Mux(
tag_compare_valid(i) && io.cpu.en && io.cpu.wen.orR && !io.cpu.tlb.uncached && state === s_idle && !tlb_fill,
io.cpu.wen,
io.cpu.wstrb,
victim.wstrb(i)
)
last_wstrb(i) := Cat(
Fill(8, data_wstrb(i)(3)),
Fill(8, data_wstrb(i)(2)),
Fill(8, data_wstrb(i)(1)),
Fill(8, data_wstrb(i)(0))
)
last_wstrb(i) := Cat((AXI_STRB_WID - 1 to 0 by -1).map(j => Fill(8, data_wstrb(i)(j))))
}
val write_buffer_axi_busy = RegInit(false.B)
@ -197,7 +192,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
write_fifo.io.deq.ready := write_fifo.io.deq.valid
when(write_fifo.io.deq.fire) {
aw.addr := write_fifo.io.deq.bits.addr
aw.size := Cat(0.U(1.W), write_fifo.io.deq.bits.size)
aw.size := write_fifo.io.deq.bits.size
w.data := write_fifo.io.deq.bits.data
w.strb := write_fifo.io.deq.bits.strb
}
@ -234,7 +229,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
io.cpu.tlb.pa
)
write_fifo.io.enq.bits.size := io.cpu.rlen
write_fifo.io.enq.bits.strb := io.cpu.wen
write_fifo.io.enq.bits.strb := io.cpu.wstrb
write_fifo.io.enq.bits.data := io.cpu.wdata
current_mmio_write_saved := true.B
@ -245,7 +240,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
}.elsewhen(!(write_fifo.io.deq.valid || write_buffer_axi_busy)) {
ar.addr := Mux(io.cpu.rlen === 2.U, Cat(io.cpu.tlb.pa(31, 2), 0.U(2.W)), io.cpu.tlb.pa)
ar.len := 0.U
ar.size := Cat(0.U(1.W), io.cpu.rlen)
ar.size := io.cpu.rlen
arvalid := true.B
state := s_uncached
rready := true.B
@ -316,7 +311,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
when(!aw_handshake) {
aw.addr := Cat(tag(dirty(fset)(1)), fset, 0.U(6.W))
aw.len := 15.U
aw.size := 2.U(3.W)
aw.size := "b011".U // 8 字节
awvalid := true.B
w.data := data(dirty(fset)(1))
w.strb := 15.U
@ -368,7 +363,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
when(!aw_handshake) {
aw.addr := Cat(tag(lru(pset)), pset, 0.U(6.W))
aw.len := 15.U
aw.size := 2.U(3.W)
aw.size := "b011".U // 8 字节
awvalid := true.B
aw_handshake := true.B
w.data := data(lru(pset))
@ -402,11 +397,11 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
when(!ar_handshake) {
ar.addr := Cat(io.cpu.tlb.pa(31, 6), 0.U(6.W))
ar.len := 15.U
ar.size := 2.U(3.W)
ar.size := "b011".U // 8 字节
arvalid := true.B
rready := true.B
ar_handshake := true.B
victim.wstrb(lru(pset)) := 15.U
victim.wstrb(lru(pset)) := "hff".U
tag_wstrb(lru(pset)) := true.B
tag_wdata := io.cpu.tlb.pa(31, 12)
}

2
chisel/playground/src/defines/Bundles.scala
View File

@ -121,7 +121,7 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
// cpu to dcache
class Cache_DCache extends Bundle {
val addr = Output(UInt(DATA_ADDR_WID.W))
val rlen = Output(UInt(2.W))
val rlen = Output(UInt(AXI_LEN_WID.W))
val en = Output(Bool())
val wen = Output(Bool())
val wdata = Output(UInt(XLEN.W))