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fix(tlb): 修复数据宽度问题

This commit is contained in:
Liphen 2023-12-25 14:01:31 +08:00
parent e646ee4a4c
commit e1639e6f8b
3 changed files with 35 additions and 14 deletions
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12
chisel/playground/src/cache/mmu/DTlbL1.scala vendored
View File

@ -4,6 +4,7 @@ import chisel3._
import chisel3.util._
import cpu.defines._
import cpu.defines.Const._
import cpu.CacheConfig
class DTlbL1 extends Module {
val io = IO(new Bundle {
@ -11,10 +12,17 @@ class DTlbL1 extends Module {
val addr = Input(UInt(DATA_ADDR_WID.W))
})
val cacheConfig = CacheConfig("dcache")
io.cache.uncached := AddressSpace.isMMIO(io.addr)
io.cache.translation_ok := true.B
io.cache.hit := true.B
io.cache.tlb1_ok := true.B
io.cache.tag := io.addr(XLEN - 1, 12)
io.cache.pa := Cat(io.cache.tag, io.addr(11, 0))
io.cache.tag := io.addr(PADDR_WID - 1, cacheConfig.offsetWidth + cacheConfig.indexWidth)
io.cache.pa := Cat(io.cache.tag, io.addr(cacheConfig.offsetWidth + cacheConfig.indexWidth - 1, 0))
println("----------------------------------------")
println("DTlbL1")
println("tag from " + (PADDR_WID - 1) + " to " + (cacheConfig.offsetWidth + cacheConfig.indexWidth))
println("----------------------------------------")
}

12
chisel/playground/src/cache/mmu/ITlbL1.scala vendored
View File

@ -4,6 +4,7 @@ import chisel3._
import chisel3.util._
import cpu.defines._
import cpu.defines.Const._
import cpu.CacheConfig
class ITlbL1 extends Module {
val io = IO(new Bundle {
@ -11,9 +12,16 @@ class ITlbL1 extends Module {
val cache = new Tlb_ICache()
})
val cacheConfig = CacheConfig("icache")
io.cache.uncached := AddressSpace.isMMIO(io.addr)
io.cache.translation_ok := true.B
io.cache.hit := true.B
io.cache.tag := io.addr(XLEN - 1, 12)
io.cache.pa := Cat(io.cache.tag, io.addr(11, 0))
io.cache.tag := io.addr(PADDR_WID - 1, cacheConfig.offsetWidth + cacheConfig.indexWidth)
io.cache.pa := Cat(io.cache.tag, io.addr(cacheConfig.offsetWidth + cacheConfig.indexWidth - 1, 0))
println("----------------------------------------")
println("ITlbL1")
println("tag from " + (PADDR_WID - 1) + " to " + (cacheConfig.offsetWidth + cacheConfig.indexWidth))
println("----------------------------------------")
}

25
chisel/playground/src/defines/TlbBundles.scala
View File

@ -2,6 +2,8 @@ package cpu.defines
import chisel3._
import chisel3.util._
import cpu.defines.Const._
import cpu.CacheConfig
sealed trait Sv39Const extends CoreParameter {
val PAddrBits = PADDR_WID
@ -113,23 +115,26 @@ sealed trait Sv39Const extends CoreParameter {
}
class Tlb_ICache extends Bundle {
val fill = Input(Bool())
val icache_is_save = Input(Bool())
val uncached = Output(Bool())
val cacheConfig = CacheConfig("icache")
val fill = Input(Bool())
val uncached = Output(Bool())
val translation_ok = Output(Bool())
val hit = Output(Bool())
val tag = Output(UInt(20.W))
val pa = Output(UInt(32.W))
val tag = Output(UInt(cacheConfig.tagWidth.W))
val pa = Output(UInt(PADDR_WID.W))
}
class Tlb_DCache extends Bundle {
val fill = Input(Bool())
val uncached = Output(Bool())
val tlb1_ok = Output(Bool())
val cacheConfig = CacheConfig("dcache")
val fill = Input(Bool())
val uncached = Output(Bool())
val tlb1_ok = Output(Bool())
val translation_ok = Output(Bool())
val hit = Output(Bool())
val tag = Output(UInt(20.W))
val pa = Output(UInt(32.W))
val tag = Output(UInt(cacheConfig.tagWidth.W))
val pa = Output(UInt(PADDR_WID.W))
}