From e1639e6f8bdfa8f47d1931f52cbef4ac8526b24e Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Mon, 25 Dec 2023 14:01:31 +0800
Subject: [PATCH] =?UTF-8?q?fix(tlb):=20=E4=BF=AE=E5=A4=8D=E6=95=B0?=
 =?UTF-8?q?=E6=8D=AE=E5=AE=BD=E5=BA=A6=E9=97=AE=E9=A2=98?=
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---
 chisel/playground/src/cache/mmu/DTlbL1.scala  | 12 +++++++--
 chisel/playground/src/cache/mmu/ITlbL1.scala  | 12 +++++++--
 .../playground/src/defines/TlbBundles.scala   | 25 +++++++++++--------
 3 files changed, 35 insertions(+), 14 deletions(-)

diff --git a/chisel/playground/src/cache/mmu/DTlbL1.scala b/chisel/playground/src/cache/mmu/DTlbL1.scala
index 6d21f7b..61f3bdd 100644
--- a/chisel/playground/src/cache/mmu/DTlbL1.scala
+++ b/chisel/playground/src/cache/mmu/DTlbL1.scala
@@ -4,6 +4,7 @@ import chisel3._
 import chisel3.util._
 import cpu.defines._
 import cpu.defines.Const._
+import cpu.CacheConfig
 
 class DTlbL1 extends Module {
   val io = IO(new Bundle {
@@ -11,10 +12,17 @@ class DTlbL1 extends Module {
     val addr  = Input(UInt(DATA_ADDR_WID.W))
   })
 
+  val cacheConfig = CacheConfig("dcache")
+
   io.cache.uncached       := AddressSpace.isMMIO(io.addr)
   io.cache.translation_ok := true.B
   io.cache.hit            := true.B
   io.cache.tlb1_ok        := true.B
-  io.cache.tag            := io.addr(XLEN - 1, 12)
-  io.cache.pa             := Cat(io.cache.tag, io.addr(11, 0))
+  io.cache.tag            := io.addr(PADDR_WID - 1, cacheConfig.offsetWidth + cacheConfig.indexWidth)
+  io.cache.pa             := Cat(io.cache.tag, io.addr(cacheConfig.offsetWidth + cacheConfig.indexWidth - 1, 0))
+
+  println("----------------------------------------")
+  println("DTlbL1")
+  println("tag from " + (PADDR_WID - 1) + " to " + (cacheConfig.offsetWidth + cacheConfig.indexWidth))
+  println("----------------------------------------")
 }
diff --git a/chisel/playground/src/cache/mmu/ITlbL1.scala b/chisel/playground/src/cache/mmu/ITlbL1.scala
index 375fb9b..39cd818 100644
--- a/chisel/playground/src/cache/mmu/ITlbL1.scala
+++ b/chisel/playground/src/cache/mmu/ITlbL1.scala
@@ -4,6 +4,7 @@ import chisel3._
 import chisel3.util._
 import cpu.defines._
 import cpu.defines.Const._
+import cpu.CacheConfig
 
 class ITlbL1 extends Module {
   val io = IO(new Bundle {
@@ -11,9 +12,16 @@ class ITlbL1 extends Module {
     val cache = new Tlb_ICache()
   })
 
+  val cacheConfig = CacheConfig("icache")
+
   io.cache.uncached       := AddressSpace.isMMIO(io.addr)
   io.cache.translation_ok := true.B
   io.cache.hit            := true.B
-  io.cache.tag            := io.addr(XLEN - 1, 12)
-  io.cache.pa             := Cat(io.cache.tag, io.addr(11, 0))
+  io.cache.tag            := io.addr(PADDR_WID - 1, cacheConfig.offsetWidth + cacheConfig.indexWidth)
+  io.cache.pa             := Cat(io.cache.tag, io.addr(cacheConfig.offsetWidth + cacheConfig.indexWidth - 1, 0))
+
+  println("----------------------------------------")
+  println("ITlbL1")
+  println("tag from " + (PADDR_WID - 1) + " to " + (cacheConfig.offsetWidth + cacheConfig.indexWidth))
+  println("----------------------------------------")
 }
diff --git a/chisel/playground/src/defines/TlbBundles.scala b/chisel/playground/src/defines/TlbBundles.scala
index a6e209b..762eb1d 100644
--- a/chisel/playground/src/defines/TlbBundles.scala
+++ b/chisel/playground/src/defines/TlbBundles.scala
@@ -2,6 +2,8 @@ package cpu.defines
 
 import chisel3._
 import chisel3.util._
+import cpu.defines.Const._
+import cpu.CacheConfig
 
 sealed trait Sv39Const extends CoreParameter {
   val PAddrBits = PADDR_WID
@@ -113,23 +115,26 @@ sealed trait Sv39Const extends CoreParameter {
 }
 
 class Tlb_ICache extends Bundle {
-  val fill           = Input(Bool())
-  val icache_is_save = Input(Bool())
-  val uncached       = Output(Bool())
+  val cacheConfig = CacheConfig("icache")
+
+  val fill     = Input(Bool())
+  val uncached = Output(Bool())
 
   val translation_ok = Output(Bool())
   val hit            = Output(Bool())
-  val tag            = Output(UInt(20.W))
-  val pa             = Output(UInt(32.W))
+  val tag            = Output(UInt(cacheConfig.tagWidth.W))
+  val pa             = Output(UInt(PADDR_WID.W))
 }
 
 class Tlb_DCache extends Bundle {
-  val fill           = Input(Bool())
-  val uncached       = Output(Bool())
-  val tlb1_ok        = Output(Bool())
+  val cacheConfig = CacheConfig("dcache")
+
+  val fill     = Input(Bool())
+  val uncached = Output(Bool())
+  val tlb1_ok  = Output(Bool())
 
   val translation_ok = Output(Bool())
   val hit            = Output(Bool())
-  val tag            = Output(UInt(20.W))
-  val pa             = Output(UInt(32.W))
+  val tag            = Output(UInt(cacheConfig.tagWidth.W))
+  val pa             = Output(UInt(PADDR_WID.W))
 }