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refactor: decoder级重命名为decode

This commit is contained in:
Liphen 2024-01-07 16:57:36 +08:00
parent 60b247c5ec
commit 08def4d1a0
20 changed files with 137 additions and 139 deletions
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40
chisel/playground/src/Core.scala
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@ -7,7 +7,7 @@ import chisel3.internal.DontCareBinding
import defines._
import defines.Const._
import pipeline.fetch._
import pipeline.decoder._
import pipeline.decode._
import pipeline.execute._
import pipeline.memory._
import pipeline.writeback._
@ -28,7 +28,7 @@ class Core(implicit val cpuConfig: CpuConfig) extends Module {
val fetchUnit = Module(new FetchUnit()).io
val bpu = Module(new BranchPredictorUnit()).io
val instFifo = Module(new InstFifo()).io
val decoderUnit = Module(new DecoderUnit()).io
val decodeUnit = Module(new DecodeUnit()).io
val regfile = Module(new ARegFile()).io
val executeStage = Module(new ExecuteStage()).io
val executeUnit = Module(new ExecuteUnit()).io
@ -48,7 +48,7 @@ class Core(implicit val cpuConfig: CpuConfig) extends Module {
dtlbL1.cache <> io.data.tlb
dtlbL1.csr <> csr.tlb
ctrl.decoderUnit <> decoderUnit.ctrl
ctrl.decodeUnit <> decodeUnit.ctrl
ctrl.executeUnit <> executeUnit.ctrl
ctrl.memoryUnit <> memoryUnit.ctrl
ctrl.writeBackUnit <> writeBackUnit.ctrl
@ -56,7 +56,7 @@ class Core(implicit val cpuConfig: CpuConfig) extends Module {
fetchUnit.memory <> memoryUnit.fetchUnit
fetchUnit.execute <> executeUnit.fetchUnit
fetchUnit.decoder <> decoderUnit.fetchUnit
fetchUnit.decode <> decodeUnit.fetchUnit
fetchUnit.instFifo.full := instFifo.full
fetchUnit.iCache.inst_valid := io.inst.inst_valid
io.inst.addr(0) := fetchUnit.iCache.pc
@ -65,12 +65,12 @@ class Core(implicit val cpuConfig: CpuConfig) extends Module {
io.inst.addr(i) := fetchUnit.iCache.pc_next + ((i - 1) * 4).U
}
bpu.decoder <> decoderUnit.bpu
bpu.decode <> decodeUnit.bpu
bpu.execute <> executeUnit.bpu
instFifo.do_flush := ctrl.decoderUnit.do_flush
instFifo.ren <> decoderUnit.instFifo.allow_to_go
decoderUnit.instFifo.inst <> instFifo.read
instFifo.do_flush := ctrl.decodeUnit.do_flush
instFifo.ren <> decodeUnit.instFifo.allow_to_go
decodeUnit.instFifo.inst <> instFifo.read
for (i <- 0 until cpuConfig.instFetchNum) {
instFifo.write(i).pht_index := bpu.instBuffer.pht_index(i)
@ -81,25 +81,25 @@ class Core(implicit val cpuConfig: CpuConfig) extends Module {
instFifo.write(i).acc_err := io.inst.acc_err
}
decoderUnit.instFifo.info.empty := instFifo.empty
decoderUnit.instFifo.info.almost_empty := instFifo.almost_empty
decoderUnit.regfile <> regfile.read
decodeUnit.instFifo.info.empty := instFifo.empty
decodeUnit.instFifo.info.almost_empty := instFifo.almost_empty
decodeUnit.regfile <> regfile.read
for (i <- 0 until (cpuConfig.commitNum)) {
decoderUnit.forward(i).exe := executeUnit.decoderUnit.forward(i).exe
decoderUnit.forward(i).mem_wreg := executeUnit.decoderUnit.forward(i).exe_mem_wreg
decoderUnit.forward(i).mem := memoryUnit.decoderUnit(i)
decodeUnit.forward(i).exe := executeUnit.decodeUnit.forward(i).exe
decodeUnit.forward(i).mem_wreg := executeUnit.decodeUnit.forward(i).exe_mem_wreg
decodeUnit.forward(i).mem := memoryUnit.decodeUnit(i)
}
decoderUnit.csr <> csr.decoderUnit
decoderUnit.executeStage <> executeStage.decoderUnit
decodeUnit.csr <> csr.decodeUnit
decodeUnit.executeStage <> executeStage.decodeUnit
executeStage.ctrl.clear(0) := ctrl.memoryUnit.flush ||
ctrl.executeUnit.do_flush && ctrl.executeUnit.allow_to_go ||
!ctrl.decoderUnit.allow_to_go && ctrl.executeUnit.allow_to_go
!ctrl.decodeUnit.allow_to_go && ctrl.executeUnit.allow_to_go
executeStage.ctrl.clear(1) := ctrl.memoryUnit.flush ||
(ctrl.executeUnit.do_flush && decoderUnit.instFifo.allow_to_go(1)) ||
(ctrl.executeUnit.allow_to_go && !decoderUnit.instFifo.allow_to_go(1))
(ctrl.executeUnit.do_flush && decodeUnit.instFifo.allow_to_go(1)) ||
(ctrl.executeUnit.allow_to_go && !decodeUnit.instFifo.allow_to_go(1))
executeStage.ctrl.allow_to_go(0) := ctrl.executeUnit.allow_to_go
executeStage.ctrl.allow_to_go(1) := decoderUnit.instFifo.allow_to_go(1)
executeStage.ctrl.allow_to_go(1) := decodeUnit.instFifo.allow_to_go(1)
executeUnit.executeStage <> executeStage.executeUnit
executeUnit.csr <> csr.executeUnit

4
chisel/playground/src/CpuConfig.scala
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@ -52,8 +52,8 @@ case class CacheConfig(
val bankIndexWidth = log2Ceil(nbank) // bank index的位宽
val bankOffsetWidth = log2Ceil(bytesPerBank) // bank offset的位宽
val offsetWidth = bankIndexWidth + bankOffsetWidth // offset的位宽
val tagWidth = PADDR_WID - offsetLen // tag的位宽
require(offsetWidth + indexWidth == offsetLen) // offsetLen是页内偏移的位宽，为简化设计，这里直接保证每路容量等于页大小
val tagWidth = PADDR_WID - pageOffsetLen // tag的位宽
require(offsetWidth + indexWidth == pageOffsetLen) // offsetLen是页内偏移的位宽，为简化设计，这里直接保证每路容量等于页大小
require(isPow2(nindex))
require(isPow2(nway))
require(isPow2(nbank))

4
chisel/playground/src/cache/mmu/DTlb.scala vendored
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@ -27,7 +27,7 @@ class DTlb extends Module with Sv39Const {
io.cache.uncached := AddressSpace.isMMIO(io.addr)
io.cache.translation_ok := true.B
io.cache.hit_L2 := true.B
io.cache.ptag := io.addr(PADDR_WID - 1, offsetLen)
io.cache.paddr := Cat(io.cache.ptag, io.addr(offsetLen - 1, 0))
io.cache.ptag := io.addr(PADDR_WID - 1, pageOffsetLen)
io.cache.paddr := Cat(io.cache.ptag, io.addr(pageOffsetLen - 1, 0))
}

7
chisel/playground/src/cache/mmu/ITlb.scala vendored
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@ -17,7 +17,7 @@ class Tlb_ICache extends Bundle {
val paddr = Output(UInt(PADDR_WID.W))
}
class ITlb extends Module with Sv39Const with HasCSRConst {
class ITlb extends Module with HasTlbConst with HasCSRConst {
val io = IO(new Bundle {
val addr = Input(UInt(XLEN.W))
val cache = new Tlb_ICache()
@ -29,11 +29,12 @@ class ITlb extends Module with Sv39Const with HasCSRConst {
val mode = WireInit(io.csr.mode)
val vm_enabled = (satp.asTypeOf(satpBundle).mode === 8.U) && (mode < ModeM)
val itlb = RegInit(0.U.asTypeOf(tlbBundle))
io.cache.uncached := AddressSpace.isMMIO(io.addr)
io.cache.translation_ok := !vm_enabled
io.cache.hit_L2 := true.B
io.cache.ptag := Mux(vm_enabled, DontCare, io.addr(PADDR_WID - 1, offsetLen))
io.cache.paddr := Cat(io.cache.ptag, io.addr(offsetLen - 1, 0))
io.cache.ptag := Mux(vm_enabled, DontCare, io.addr(PADDR_WID - 1, pageOffsetLen))
io.cache.paddr := Cat(io.cache.ptag, io.addr(pageOffsetLen - 1, 0))
}

14
chisel/playground/src/ctrl/Ctrl.scala
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@ -10,31 +10,31 @@ class Ctrl(implicit val cpuConfig: CpuConfig) extends Module {
val io = IO(new Bundle {
val cacheCtrl = Flipped(new CacheCtrl())
val fetchUnit = Flipped(new FetchUnitCtrl())
val decoderUnit = Flipped(new DecoderUnitCtrl())
val decodeUnit = Flipped(new DecodeUnitCtrl())
val executeUnit = Flipped(new ExecuteCtrl())
val memoryUnit = Flipped(new MemoryCtrl())
val writeBackUnit = Flipped(new WriteBackCtrl())
})
val inst0_lw_stall = (io.executeUnit.inst(0).mem_wreg) && io.executeUnit.inst(0).reg_waddr.orR &&
(io.decoderUnit.inst0.src1.ren && io.decoderUnit.inst0.src1.raddr === io.executeUnit.inst(0).reg_waddr ||
io.decoderUnit.inst0.src2.ren && io.decoderUnit.inst0.src2.raddr === io.executeUnit.inst(0).reg_waddr)
(io.decodeUnit.inst0.src1.ren && io.decodeUnit.inst0.src1.raddr === io.executeUnit.inst(0).reg_waddr ||
io.decodeUnit.inst0.src2.ren && io.decodeUnit.inst0.src2.raddr === io.executeUnit.inst(0).reg_waddr)
val inst1_lw_stall = (io.executeUnit.inst(1).mem_wreg) && io.executeUnit.inst(1).reg_waddr.orR &&
(io.decoderUnit.inst0.src1.ren && io.decoderUnit.inst0.src1.raddr === io.executeUnit.inst(1).reg_waddr ||
io.decoderUnit.inst0.src2.ren && io.decoderUnit.inst0.src2.raddr === io.executeUnit.inst(1).reg_waddr)
(io.decodeUnit.inst0.src1.ren && io.decodeUnit.inst0.src1.raddr === io.executeUnit.inst(1).reg_waddr ||
io.decodeUnit.inst0.src2.ren && io.decodeUnit.inst0.src2.raddr === io.executeUnit.inst(1).reg_waddr)
val lw_stall = inst0_lw_stall || inst1_lw_stall
// TODO: 这里的stall信号可以改进，尝试让前后端完全解耦
val longest_stall =
io.executeUnit.fu_stall || io.cacheCtrl.iCache_stall || io.memoryUnit.mem_stall
io.fetchUnit.allow_to_go := !io.cacheCtrl.iCache_stall
io.decoderUnit.allow_to_go := !(lw_stall || longest_stall)
io.decodeUnit.allow_to_go := !(lw_stall || longest_stall)
io.executeUnit.allow_to_go := !longest_stall
io.memoryUnit.allow_to_go := !longest_stall
io.writeBackUnit.allow_to_go := !longest_stall || io.memoryUnit.flush
io.fetchUnit.do_flush := false.B
io.decoderUnit.do_flush := io.memoryUnit.flush || io.executeUnit.flush || io.decoderUnit.branch
io.decodeUnit.do_flush := io.memoryUnit.flush || io.executeUnit.flush || io.decodeUnit.branch
io.executeUnit.do_flush := io.memoryUnit.flush || io.executeUnit.flush
io.memoryUnit.do_flush := io.memoryUnit.flush
io.writeBackUnit.do_flush := false.B

2
chisel/playground/src/defines/Bundles.scala
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@ -62,7 +62,7 @@ class FetchUnitCtrl extends Bundle {
val do_flush = Input(Bool())
}
class DecoderUnitCtrl extends Bundle {
class DecodeUnitCtrl extends Bundle {
val inst0 = Output(new Bundle {
val src1 = new SrcReadSignal()
val src2 = new SrcReadSignal()

44
chisel/playground/src/defines/TlbBundles.scala
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@ -7,20 +7,18 @@ import cpu.CacheConfig
import cpu.TLBConfig
trait Sv39Const extends CoreParameter {
val PAddrBits = PADDR_WID
val Level = 3
val offsetLen = 12
val ppn0Len = 9
val ppn1Len = 9
val ppn2Len = PAddrBits - offsetLen - ppn0Len - ppn1Len // 2
val ppnLen = ppn2Len + ppn1Len + ppn0Len
val vpn2Len = 9
val vpn1Len = 9
val vpn0Len = 9
val vpnLen = vpn2Len + vpn1Len + vpn0Len
val PAddrBits = PADDR_WID // 32
val level = 3
val pageOffsetLen = 12 // 页面大小为4KB，对应的偏移量长度为12位
val ppn0Len = 9
val ppn1Len = 9
val ppn2Len = PAddrBits - pageOffsetLen - ppn0Len - ppn1Len // 2
val ppnLen = ppn2Len + ppn1Len + ppn0Len // 20
val vpn2Len = 9
val vpn1Len = 9
val vpn0Len = 9
val vpnLen = vpn2Len + vpn1Len + vpn0Len // 27
//val paddrLen = PAddrBits
//val vaddrLen = VAddrBits
val satpLen = XLEN
val satpModeLen = 4
val asidLen = 16
@ -28,25 +26,23 @@ trait Sv39Const extends CoreParameter {
val ptEntryLen = XLEN
val satpResLen = XLEN - ppnLen - satpModeLen - asidLen
//val vaResLen = 25 // unused
//val paResLen = 25 // unused
val pteResLen = XLEN - ppnLen - 2 - flagLen
val pteResLen = XLEN - ppnLen - 2 - flagLen
def vaBundle = new Bundle {
val vpn2 = UInt(vpn2Len.W)
val vpn1 = UInt(vpn1Len.W)
val vpn0 = UInt(vpn0Len.W)
val offset = UInt(offsetLen.W)
val offset = UInt(pageOffsetLen.W)
}
def vaBundle2 = new Bundle {
val vpn = UInt(vpnLen.W)
val offset = UInt(offsetLen.W)
val offset = UInt(pageOffsetLen.W)
}
def vaBundle3 = new Bundle {
val vpn = UInt(vpnLen.W)
val offset = UInt(offsetLen.W)
val offset = UInt(pageOffsetLen.W)
}
def vpnBundle = new Bundle {
@ -59,12 +55,12 @@ trait Sv39Const extends CoreParameter {
val ppn2 = UInt(ppn2Len.W)
val ppn1 = UInt(ppn1Len.W)
val ppn0 = UInt(ppn0Len.W)
val offset = UInt(offsetLen.W)
val offset = UInt(pageOffsetLen.W)
}
def paBundle2 = new Bundle {
val ppn = UInt(ppnLen.W)
val offset = UInt(offsetLen.W)
val offset = UInt(pageOffsetLen.W)
}
def paddrApply(ppn: UInt, vpnn: UInt): UInt = {
@ -106,7 +102,7 @@ trait Sv39Const extends CoreParameter {
}
def maskPaddr(ppn: UInt, vaddr: UInt, mask: UInt) = {
MaskData(vaddr, Cat(ppn, 0.U(offsetLen.W)), Cat(Fill(ppn2Len, 1.U(1.W)), mask, 0.U(offsetLen.W)))
MaskData(vaddr, Cat(ppn, 0.U(pageOffsetLen.W)), Cat(Fill(ppn2Len, 1.U(1.W)), mask, 0.U(pageOffsetLen.W)))
}
def MaskEQ(mask: UInt, pattern: UInt, vpn: UInt) = {
@ -120,7 +116,7 @@ trait HasTlbConst extends Sv39Const {
val maskLen = vpn0Len + vpn1Len // 18
val metaLen = vpnLen + asidLen + maskLen + flagLen // 27 + 16 + 18 + 8 = 69, is asid necessary
val dataLen = ppnLen + PAddrBits //
val dataLen = ppnLen + PAddrBits // 20 + 32 = 52
val tlbLen = metaLen + dataLen
val nway = tlbConfig.nway
val nindex = tlbConfig.nindex
@ -130,7 +126,7 @@ trait HasTlbConst extends Sv39Const {
def vaddrTlbBundle = new Bundle {
val tag = UInt(tagWid.W)
val index = UInt(indexWid.W)
val off = UInt(offsetLen.W)
val off = UInt(pageOffsetLen.W)
}
def metaBundle = new Bundle {

2
chisel/playground/src/pipeline/decoder/ARegfile.scala → chisel/playground/src/pipeline/decode/ARegfile.scala
View File

@ -1,4 +1,4 @@
package cpu.pipeline.decoder
package cpu.pipeline.decode
import chisel3._
import chisel3.util._

20
chisel/playground/src/pipeline/decoder/DecoderUnit.scala → chisel/playground/src/pipeline/decode/DecodeUnit.scala
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@ -1,4 +1,4 @@
package cpu.pipeline.decoder
package cpu.pipeline.decode
import chisel3._
import chisel3.util._
@ -6,11 +6,11 @@ import chisel3.util.experimental.BoringUtils
import cpu.defines._
import cpu.defines.Const._
import cpu.{BranchPredictorConfig, CpuConfig}
import cpu.pipeline.execute.DecoderUnitExecuteUnit
import cpu.pipeline.execute.DecodeUnitExecuteUnit
import cpu.pipeline.fetch.BufferUnit
import cpu.pipeline.execute
class InstFifoDecoderUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
class InstFifoDecodeUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
val allow_to_go = Output(Vec(cpuConfig.decoderNum, Bool()))
val inst = Input(Vec(cpuConfig.decoderNum, new BufferUnit()))
val info = Input(new Bundle {
@ -19,7 +19,7 @@ class InstFifoDecoderUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
})
}
class DataForwardToDecoderUnit extends Bundle {
class DataForwardToDecodeUnit extends Bundle {
val exe = new RegWrite()
val mem_wreg = Bool()
val mem = new RegWrite()
@ -37,21 +37,21 @@ class DecoderBranchPredictorUnit extends Bundle {
val update_pht_index = Input(UInt(bpuConfig.phtDepth.W))
}
class DecoderUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExceptionNO with HasCSRConst {
class DecodeUnit(implicit val cpuConfig: CpuConfig) extends Module with HasExceptionNO with HasCSRConst {
val io = IO(new Bundle {
// 输入
val instFifo = new InstFifoDecoderUnit()
val instFifo = new InstFifoDecodeUnit()
val regfile = Vec(cpuConfig.decoderNum, new Src12Read())
val forward = Input(Vec(cpuConfig.commitNum, new DataForwardToDecoderUnit()))
val csr = Input(new execute.CsrDecoderUnit())
val forward = Input(Vec(cpuConfig.commitNum, new DataForwardToDecodeUnit()))
val csr = Input(new execute.CsrDecodeUnit())
// 输出
val fetchUnit = new Bundle {
val branch = Output(Bool())
val target = Output(UInt(XLEN.W))
}
val bpu = new DecoderBranchPredictorUnit()
val executeStage = Output(new DecoderUnitExecuteUnit())
val ctrl = new DecoderUnitCtrl()
val executeStage = Output(new DecodeUnitExecuteUnit())
val ctrl = new DecodeUnitCtrl()
})
val decoder = Seq.fill(cpuConfig.decoderNum)(Module(new Decoder()))

2
chisel/playground/src/pipeline/decoder/Decoder.scala → chisel/playground/src/pipeline/decode/Decoder.scala
View File

@ -1,4 +1,4 @@
package cpu.pipeline.decoder
package cpu.pipeline.decode
import chisel3._
import chisel3.util._

4
chisel/playground/src/pipeline/decoder/ForwardCtrl.scala → chisel/playground/src/pipeline/decode/ForwardCtrl.scala
View File

@ -1,4 +1,4 @@
package cpu.pipeline.decoder
package cpu.pipeline.decode
import chisel3._
import chisel3.util._
@ -10,7 +10,7 @@ import cpu.CpuConfig
class ForwardCtrl(implicit val cpuConfig: CpuConfig) extends Module {
val io = IO(new Bundle {
val in = Input(new Bundle {
val forward = Vec(cpuConfig.commitNum, new DataForwardToDecoderUnit())
val forward = Vec(cpuConfig.commitNum, new DataForwardToDecodeUnit())
val regfile = Vec(cpuConfig.decoderNum, new Src12Read())
})
val out = Output(new Bundle {

2
chisel/playground/src/pipeline/decoder/Issue.scala → chisel/playground/src/pipeline/decode/Issue.scala
View File

@ -1,4 +1,4 @@
package cpu.pipeline.decoder
package cpu.pipeline.decode
import chisel3._
import chisel3.util._

4
chisel/playground/src/pipeline/decoder/JumpCtrl.scala → chisel/playground/src/pipeline/decode/JumpCtrl.scala
View File

@ -1,4 +1,4 @@
package cpu.pipeline.decoder
package cpu.pipeline.decode
import chisel3._
import chisel3.util._
@ -13,7 +13,7 @@ class JumpCtrl(implicit val cpuConfig: CpuConfig) extends Module {
val pc = UInt(XLEN.W)
val info = new InstInfo()
val src_info = new SrcInfo()
val forward = Vec(cpuConfig.commitNum, new DataForwardToDecoderUnit())
val forward = Vec(cpuConfig.commitNum, new DataForwardToDecodeUnit())
})
val out = Output(new Bundle {
val jump_register = Bool()

32
chisel/playground/src/pipeline/execute/ExecuteStage.scala
View File

@ -7,11 +7,11 @@ import cpu.defines.Const._
import cpu.{BranchPredictorConfig, CpuConfig}
class IdExeInst0 extends Bundle {
val cpuConfig = new BranchPredictorConfig()
val pc = UInt(XLEN.W)
val info = new InstInfo()
val src_info = new SrcInfo()
val ex = new ExceptionInfo()
val cpuConfig = new BranchPredictorConfig()
val pc = UInt(XLEN.W)
val info = new InstInfo()
val src_info = new SrcInfo()
val ex = new ExceptionInfo()
val jb_info = new Bundle {
// jump ctrl
val jump_regiser = Bool()
@ -24,13 +24,13 @@ class IdExeInst0 extends Bundle {
}
class IdExeInst1 extends Bundle {
val pc = UInt(XLEN.W)
val info = new InstInfo()
val src_info = new SrcInfo()
val ex = new ExceptionInfo()
val pc = UInt(XLEN.W)
val info = new InstInfo()
val src_info = new SrcInfo()
val ex = new ExceptionInfo()
}
class DecoderUnitExecuteUnit extends Bundle {
class DecodeUnitExecuteUnit extends Bundle {
val inst0 = new IdExeInst0()
val inst1 = new IdExeInst1()
}
@ -38,11 +38,11 @@ class DecoderUnitExecuteUnit extends Bundle {
class ExecuteStage(implicit val cpuConfig: CpuConfig) extends Module {
val io = IO(new Bundle {
val ctrl = Input(new Bundle {
val allow_to_go = Vec(cpuConfig.decoderNum,Bool())
val clear = Vec(cpuConfig.decoderNum, Bool())
val allow_to_go = Vec(cpuConfig.decoderNum, Bool())
val clear = Vec(cpuConfig.decoderNum, Bool())
})
val decoderUnit = Input(new DecoderUnitExecuteUnit())
val executeUnit = Output(new DecoderUnitExecuteUnit())
val decodeUnit = Input(new DecodeUnitExecuteUnit())
val executeUnit = Output(new DecodeUnitExecuteUnit())
})
val inst0 = RegInit(0.U.asTypeOf(new IdExeInst0()))
@ -51,13 +51,13 @@ class ExecuteStage(implicit val cpuConfig: CpuConfig) extends Module {
when(io.ctrl.clear(0)) {
inst0 := 0.U.asTypeOf(new IdExeInst0())
}.elsewhen(io.ctrl.allow_to_go(0)) {
inst0 := io.decoderUnit.inst0
inst0 := io.decodeUnit.inst0
}
when(io.ctrl.clear(1)) {
inst1 := 0.U.asTypeOf(new IdExeInst1())
}.elsewhen(io.ctrl.allow_to_go(1)) {
inst1 := io.decoderUnit.inst1
inst1 := io.decodeUnit.inst1
}
io.executeUnit.inst0 := inst0

22
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
View File

@ -5,21 +5,21 @@ import chisel3.util._
import cpu.CpuConfig
import cpu.defines._
import cpu.defines.Const._
import cpu.pipeline.decoder.RegWrite
import cpu.pipeline.decode.RegWrite
import cpu.pipeline.memory.ExecuteUnitMemoryUnit
import cpu.pipeline.fetch.ExecuteUnitBranchPredictor
class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module {
val io = IO(new Bundle {
val ctrl = new ExecuteCtrl()
val executeStage = Input(new DecoderUnitExecuteUnit())
val executeStage = Input(new DecodeUnitExecuteUnit())
val csr = Flipped(new CsrExecuteUnit())
val bpu = new ExecuteUnitBranchPredictor()
val fetchUnit = Output(new Bundle {
val flush = Bool()
val target = UInt(XLEN.W)
})
val decoderUnit = new Bundle {
val decodeUnit = new Bundle {
val forward = Output(
Vec(
cpuConfig.commitNum,
@ -177,13 +177,13 @@ class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module {
io.memoryStage.inst1.ex.tval := io.fetchUnit.target
}
io.decoderUnit.forward(0).exe.wen := io.memoryStage.inst0.info.reg_wen
io.decoderUnit.forward(0).exe.waddr := io.memoryStage.inst0.info.reg_waddr
io.decoderUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata(io.memoryStage.inst0.info.fusel)
io.decoderUnit.forward(0).exe_mem_wreg := io.ctrl.inst(0).mem_wreg
io.decodeUnit.forward(0).exe.wen := io.memoryStage.inst0.info.reg_wen
io.decodeUnit.forward(0).exe.waddr := io.memoryStage.inst0.info.reg_waddr
io.decodeUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata(io.memoryStage.inst0.info.fusel)
io.decodeUnit.forward(0).exe_mem_wreg := io.ctrl.inst(0).mem_wreg
io.decoderUnit.forward(1).exe.wen := io.memoryStage.inst1.info.reg_wen
io.decoderUnit.forward(1).exe.waddr := io.memoryStage.inst1.info.reg_waddr
io.decoderUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata(io.memoryStage.inst1.info.fusel)
io.decoderUnit.forward(1).exe_mem_wreg := io.ctrl.inst(1).mem_wreg
io.decodeUnit.forward(1).exe.wen := io.memoryStage.inst1.info.reg_wen
io.decodeUnit.forward(1).exe.waddr := io.memoryStage.inst1.info.reg_waddr
io.decodeUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata(io.memoryStage.inst1.info.fusel)
io.decodeUnit.forward(1).exe_mem_wreg := io.ctrl.inst(1).mem_wreg
}

8
chisel/playground/src/pipeline/execute/fu/Csr.scala
View File

@ -42,7 +42,7 @@ class CsrExecuteUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
})
}
class CsrDecoderUnit extends Bundle {
class CsrDecodeUnit extends Bundle {
val mode = Output(Priv())
val interrupt = Output(UInt(INT_WID.W))
}
@ -55,7 +55,7 @@ class CsrTlb extends Bundle {
class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
val io = IO(new Bundle {
val ext_int = Input(new ExtInterrupt())
val decoderUnit = new CsrDecoderUnit()
val decodeUnit = new CsrDecodeUnit()
val executeUnit = new CsrExecuteUnit()
val memoryUnit = new CsrMemoryUnit()
val tlb = new CsrTlb()
@ -253,7 +253,7 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
val interrupt_enable = Wire(Vec(INT_WID, Bool()))
interrupt_enable.zip(ideleg.asBools).map { case (x, y) => x := priviledgedEnableDetect(y) }
io.decoderUnit.interrupt := mie(INT_WID - 1, 0) & mip_has_interrupt.asUInt & interrupt_enable.asUInt
io.decodeUnit.interrupt := mie(INT_WID - 1, 0) & mip_has_interrupt.asUInt & interrupt_enable.asUInt
// 优先使用inst0的信息
val mem_pc = io.memoryUnit.in.pc
@ -415,7 +415,7 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
io.tlb.mode := mode
io.tlb.satp := satp
io.decoderUnit.mode := mode
io.decodeUnit.mode := mode
io.executeUnit.out.ex := io.executeUnit.in.ex
io.executeUnit.out.ex.exception(illegalInstr) :=
(illegal_addr || illegal_access) && write | io.executeUnit.in.ex.exception(illegalInstr)

37
chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala
View File

@ -4,12 +4,13 @@ import chisel3._
import chisel3.util._
import cpu.defines.Const._
import cpu._
import cpu.pipeline.decoder.Src12Read
import cpu.pipeline.decode.Src12Read
import cpu.defines.BRUOpType
import cpu.defines.FuOpType
import cpu.defines.FuType
import cpu.defines.SignedExtend
import cpu.pipeline.decoder.DecoderBranchPredictorUnit
import cpu.pipeline.decode.DecoderBranchPredictorUnit
import pipeline.decode.{DecoderBranchPredictorUnit, Src12Read}
class ExecuteUnitBranchPredictor extends Bundle {
val bpuConfig = new BranchPredictorConfig()
@ -21,7 +22,7 @@ class ExecuteUnitBranchPredictor extends Bundle {
class BranchPredictorIO(implicit cpuConfig: CpuConfig) extends Bundle {
val bpuConfig = new BranchPredictorConfig()
val decoder = Flipped(new DecoderBranchPredictorUnit())
val decode = Flipped(new DecoderBranchPredictorUnit())
val instBuffer = new Bundle {
val pc = Input(Vec(cpuConfig.instFetchNum, UInt(XLEN.W)))
@ -58,20 +59,20 @@ class GlobalBranchPredictor(
val strongly_not_taken :: weakly_not_taken :: weakly_taken :: strongly_taken :: Nil = Enum(4)
val imm = io.decoder.info.imm
val imm = io.decode.info.imm
io.decoder.branch_inst := io.decoder.info.valid &&
FuType.bru === io.decoder.info.fusel && BRUOpType.isBranch(io.decoder.info.op)
io.decoder.target := io.decoder.pc + imm
io.decode.branch_inst := io.decode.info.valid &&
FuType.bru === io.decode.info.fusel && BRUOpType.isBranch(io.decode.info.op)
io.decode.target := io.decode.pc + imm
// 局部预测模式
val bht = RegInit(VecInit(Seq.fill(1 << BHT_DEPTH)(0.U(PHT_DEPTH.W))))
val pht = RegInit(VecInit(Seq.fill(1 << PHT_DEPTH)(strongly_taken)))
val bht_index = io.decoder.pc(1 + BHT_DEPTH, 2)
val bht_index = io.decode.pc(1 + BHT_DEPTH, 2)
val pht_index = bht(bht_index)
io.decoder.branch :=
io.decoder.branch_inst && (pht(pht_index) === weakly_taken || pht(pht_index) === strongly_taken)
io.decode.branch :=
io.decode.branch_inst && (pht(pht_index) === weakly_taken || pht(pht_index) === strongly_taken)
val update_bht_index = io.execute.pc(1 + BHT_DEPTH, 2)
val update_pht_index = bht(update_bht_index)
@ -107,23 +108,23 @@ class AdaptiveTwoLevelPredictor(
val strongly_not_taken :: weakly_not_taken :: weakly_taken :: strongly_taken :: Nil = Enum(4)
val imm = io.decoder.info.imm
val imm = io.decode.info.imm
io.decoder.branch_inst := io.decoder.info.valid &&
FuType.bru === io.decoder.info.fusel && BRUOpType.isBranch(io.decoder.info.op)
io.decoder.target := io.decoder.pc + imm
io.decode.branch_inst := io.decode.info.valid &&
FuType.bru === io.decode.info.fusel && BRUOpType.isBranch(io.decode.info.op)
io.decode.target := io.decode.pc + imm
val bht = RegInit(VecInit(Seq.fill(1 << BHT_DEPTH)(0.U(PHT_DEPTH.W))))
val pht = RegInit(VecInit(Seq.fill(1 << PHT_DEPTH)(strongly_taken)))
val pht_index = io.decoder.pht_index
val pht_index = io.decode.pht_index
for (i <- 0 until cpuConfig.instFetchNum) {
io.instBuffer.pht_index(i) := bht(io.instBuffer.pc(i)(1 + BHT_DEPTH, 2))
}
io.decoder.branch :=
io.decoder.branch_inst && (pht(pht_index) === weakly_taken || pht(pht_index) === strongly_taken)
io.decoder.update_pht_index := bht(io.decoder.pc(1 + BHT_DEPTH, 2))
io.decode.branch :=
io.decode.branch_inst && (pht(pht_index) === weakly_taken || pht(pht_index) === strongly_taken)
io.decode.update_pht_index := bht(io.decode.pc(1 + BHT_DEPTH, 2))
val update_bht_index = io.execute.pc(1 + BHT_DEPTH, 2)
val update_pht_index = io.execute.update_pht_index

10
chisel/playground/src/pipeline/fetch/FetchUnit.scala
View File

@ -14,7 +14,7 @@ class FetchUnit(
val flush = Input(Bool())
val target = Input(UInt(XLEN.W))
}
val decoder = new Bundle {
val decode = new Bundle {
val branch = Input(Bool())
val target = Input(UInt(XLEN.W))
}
@ -49,10 +49,10 @@ class FetchUnit(
io.iCache.pc_next := MuxCase(
pc_next_temp,
Seq(
io.memory.flush -> io.memory.target,
io.execute.flush -> io.execute.target,
io.decoder.branch -> io.decoder.target,
io.instFifo.full -> pc
io.memory.flush -> io.memory.target,
io.execute.flush -> io.execute.target,
io.decode.branch -> io.decode.target,
io.instFifo.full -> pc
)
)
}

16
chisel/playground/src/pipeline/memory/MemoryUnit.scala
View File

@ -5,7 +5,7 @@ import chisel3.util._
import cpu.defines._
import cpu.defines.Const._
import cpu.CpuConfig
import cpu.pipeline.decoder.RegWrite
import cpu.pipeline.decode.RegWrite
import cpu.pipeline.execute.CsrMemoryUnit
import cpu.pipeline.writeback.MemoryUnitWriteBackUnit
@ -17,7 +17,7 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
val flush = Bool()
val target = UInt(XLEN.W)
})
val decoderUnit = Output(Vec(cpuConfig.commitNum, new RegWrite()))
val decodeUnit = Output(Vec(cpuConfig.commitNum, new RegWrite()))
val csr = Flipped(new CsrMemoryUnit())
val writeBackStage = Output(new MemoryUnitWriteBackUnit())
val dataMemory = new Lsu_DataMemory()
@ -93,12 +93,12 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
lsu.memoryUnit.in.lr := io.csr.out.lr
lsu.memoryUnit.in.lr_addr := io.csr.out.lr_addr
io.decoderUnit(0).wen := io.writeBackStage.inst0.info.reg_wen
io.decoderUnit(0).waddr := io.writeBackStage.inst0.info.reg_waddr
io.decoderUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.info.fusel)
io.decoderUnit(1).wen := io.writeBackStage.inst1.info.reg_wen
io.decoderUnit(1).waddr := io.writeBackStage.inst1.info.reg_waddr
io.decoderUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.info.fusel)
io.decodeUnit(0).wen := io.writeBackStage.inst0.info.reg_wen
io.decodeUnit(0).waddr := io.writeBackStage.inst0.info.reg_waddr
io.decodeUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.info.fusel)
io.decodeUnit(1).wen := io.writeBackStage.inst1.info.reg_wen
io.decodeUnit(1).waddr := io.writeBackStage.inst1.info.reg_waddr
io.decodeUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.info.fusel)
io.writeBackStage.inst0.pc := io.memoryStage.inst0.pc
io.writeBackStage.inst0.info := io.memoryStage.inst0.info

2
chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
View File

@ -4,7 +4,7 @@ import chisel3._
import chisel3.util._
import cpu.defines._
import cpu.defines.Const._
import cpu.pipeline.decoder.RegWrite
import cpu.pipeline.decode.RegWrite
import cpu.CpuConfig
class WriteBackUnit(implicit val cpuConfig: CpuConfig) extends Module {