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refactor: 修改info内信号名

This commit is contained in:
Liphen 2023-12-19 14:47:40 +08:00
parent 90efc32bca
commit 41da1f4c3e
6 changed files with 36 additions and 36 deletions
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2
chisel/difftest

@ -1 +1 @@
Subproject commit e594fb7712718f018e9acdf3d0b3cba08e5de26a
Subproject commit 08fcb9397457a58e7463f83fa3e62742783cf136

8
chisel/playground/src/defines/Bundles.scala
View File

@ -30,10 +30,10 @@ class RdInfo extends Bundle {
class InstInfo extends Bundle {
val valid = Bool()
val inst_legal = Bool()
val reg1_ren = Bool()
val reg1_raddr = UInt(REG_ADDR_WID.W)
val reg2_ren = Bool()
val reg2_raddr = UInt(REG_ADDR_WID.W)
val src1_ren = Bool()
val src1_raddr = UInt(REG_ADDR_WID.W)
val src2_ren = Bool()
val src2_raddr = UInt(REG_ADDR_WID.W)
val fusel = FuType()
val op = FuOpType()
val reg_wen = Bool()

10
chisel/playground/src/pipeline/decoder/Decoder.scala
View File

@ -38,10 +38,10 @@ class Decoder extends Module with HasInstrType {
io.out.info.valid := false.B
io.out.info.inst_legal := instrType =/= InstrN
io.out.info.reg1_ren := src1Type === SrcType.reg
io.out.info.reg1_raddr := Mux(io.out.info.reg1_ren, rs, 0.U)
io.out.info.reg2_ren := src2Type === SrcType.reg
io.out.info.reg2_raddr := Mux(io.out.info.reg2_ren, rt, 0.U)
io.out.info.src1_ren := src1Type === SrcType.reg
io.out.info.src1_raddr := Mux(io.out.info.src1_ren, rs, 0.U)
io.out.info.src2_ren := src2Type === SrcType.reg
io.out.info.src2_raddr := Mux(io.out.info.src2_ren, rt, 0.U)
io.out.info.fusel := fuType
io.out.info.op := fuOpType
io.out.info.reg_wen := isrfWen(instrType)
@ -57,5 +57,5 @@ class Decoder extends Module with HasInstrType {
InstrJ -> SignedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN)
)
)
io.out.info.inst := inst
io.out.info.inst := inst
}

24
chisel/playground/src/pipeline/decoder/DecoderUnit.scala
View File

@ -78,10 +78,10 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
issue.execute(i).reg_waddr := io.forward(i).exe.waddr
}
io.regfile(0).src1.raddr := info(0).reg1_raddr
io.regfile(0).src2.raddr := info(0).reg2_raddr
io.regfile(1).src1.raddr := info(1).reg1_raddr
io.regfile(1).src2.raddr := info(1).reg2_raddr
io.regfile(0).src1.raddr := info(0).src1_raddr
io.regfile(0).src2.raddr := info(0).src2_raddr
io.regfile(1).src1.raddr := info(1).src1_raddr
io.regfile(1).src2.raddr := info(1).src2_raddr
forwardCtrl.in.forward := io.forward
forwardCtrl.in.regfile := io.regfile
jumpCtrl.in.info := info(0)
@ -99,10 +99,10 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.bpu.info := info(0)
io.bpu.pht_index := io.instFifo.inst(0).pht_index
io.ctrl.inst0.src1.ren := info(0).reg1_ren
io.ctrl.inst0.src1.raddr := info(0).reg1_raddr
io.ctrl.inst0.src2.ren := info(0).reg2_ren
io.ctrl.inst0.src2.raddr := info(0).reg2_raddr
io.ctrl.inst0.src1.ren := info(0).src1_ren
io.ctrl.inst0.src1.raddr := info(0).src1_raddr
io.ctrl.inst0.src2.ren := info(0).src2_ren
io.ctrl.inst0.src2.raddr := info(0).src2_raddr
io.ctrl.branch := io.fetchUnit.branch
io.executeStage.inst0.pc := pc(0)
@ -110,12 +110,12 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst0.src_info.src1_data := MuxCase(
SignedExtend(pc(0), INST_ADDR_WID),
Seq(
info(0).reg1_ren -> forwardCtrl.out.inst(0).src1.rdata,
info(0).src1_ren -> forwardCtrl.out.inst(0).src1.rdata,
(info(0).inst(6, 0) === "b0110111".U) -> 0.U
)
)
io.executeStage.inst0.src_info.src2_data := Mux(
info(0).reg2_ren,
info(0).src2_ren,
forwardCtrl.out.inst(0).src2.rdata,
info(0).imm
)
@ -152,12 +152,12 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst1.src_info.src1_data := MuxCase(
SignedExtend(pc(1), INST_ADDR_WID),
Seq(
info(1).reg1_ren -> forwardCtrl.out.inst(1).src1.rdata,
info(1).src1_ren -> forwardCtrl.out.inst(1).src1.rdata,
(info(1).inst(6, 0) === "b0110111".U) -> 0.U
)
)
io.executeStage.inst1.src_info.src2_data := Mux(
info(1).reg2_ren,
info(1).src2_ren,
forwardCtrl.out.inst(1).src2.rdata,
info(1).imm
)

12
chisel/playground/src/pipeline/decoder/Issue.scala
View File

@ -40,15 +40,15 @@ class Issue(implicit val config: CpuConfig) extends Module {
// 写后读冲突
val load_stall =
io.execute(0).mem_wreg && io.execute(0).reg_waddr.orR &&
(inst1.reg1_ren && inst1.reg1_raddr === io.execute(0).reg_waddr ||
inst1.reg2_ren && inst1.reg2_raddr === io.execute(0).reg_waddr) ||
(inst1.src1_ren && inst1.src1_raddr === io.execute(0).reg_waddr ||
inst1.src2_ren && inst1.src2_raddr === io.execute(0).reg_waddr) ||
io.execute(1).mem_wreg && io.execute(1).reg_waddr.orR &&
(inst1.reg1_ren && inst1.reg1_raddr === io.execute(1).reg_waddr ||
inst1.reg2_ren && inst1.reg2_raddr === io.execute(1).reg_waddr)
(inst1.src1_ren && inst1.src1_raddr === io.execute(1).reg_waddr ||
inst1.src2_ren && inst1.src2_raddr === io.execute(1).reg_waddr)
val raw_reg =
inst0.reg_wen && inst0.reg_waddr.orR &&
(inst0.reg_waddr === inst1.reg1_raddr && inst1.reg1_ren ||
inst0.reg_waddr === inst1.reg2_raddr && inst1.reg2_ren)
(inst0.reg_waddr === inst1.src1_raddr && inst1.src1_ren ||
inst0.reg_waddr === inst1.src2_raddr && inst1.src2_ren)
val data_conflict = raw_reg || load_stall
// 指令0为bru指令

16
chisel/playground/src/pipeline/decoder/JumpCtrl.scala
View File

@ -31,16 +31,16 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module {
io.out.jump_inst := jump_inst || jump_register_inst
io.out.jump := (jump_inst || jump_register_inst && !io.out.jump_register) && valid
if (config.decoderNum == 2) {
io.out.jump_register := jump_register_inst && io.in.info.reg1_raddr.orR &&
((io.in.forward(0).exe.wen && io.in.info.reg1_raddr === io.in.forward(0).exe.waddr) ||
(io.in.forward(1).exe.wen && io.in.info.reg1_raddr === io.in.forward(1).exe.waddr) ||
(io.in.forward(0).mem.wen && io.in.info.reg1_raddr === io.in.forward(0).mem.waddr) ||
(io.in.forward(1).mem.wen && io.in.info.reg1_raddr === io.in.forward(1).mem.waddr))
io.out.jump_register := jump_register_inst && io.in.info.src1_raddr.orR &&
((io.in.forward(0).exe.wen && io.in.info.src1_raddr === io.in.forward(0).exe.waddr) ||
(io.in.forward(1).exe.wen && io.in.info.src1_raddr === io.in.forward(1).exe.waddr) ||
(io.in.forward(0).mem.wen && io.in.info.src1_raddr === io.in.forward(0).mem.waddr) ||
(io.in.forward(1).mem.wen && io.in.info.src1_raddr === io.in.forward(1).mem.waddr))
} else {
io.out.jump_register := jump_register_inst && io.in.info.reg1_raddr.orR &&
((io.in.forward(0).exe.wen && io.in.info.reg1_raddr === io.in.forward(0).exe.waddr) ||
(io.in.forward(0).mem.wen && io.in.info.reg1_raddr === io.in.forward(0).mem.waddr))
io.out.jump_register := jump_register_inst && io.in.info.src1_raddr.orR &&
((io.in.forward(0).exe.wen && io.in.info.src1_raddr === io.in.forward(0).exe.waddr) ||
(io.in.forward(0).mem.wen && io.in.info.src1_raddr === io.in.forward(0).mem.waddr))
}
io.out.jump_target := Mux(
jump_inst,