Liphen
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9d36be8d8d
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更新README
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2024-06-15 11:55:04 +08:00 |
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Liphen
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4666edd560
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完成挖空，作为演示代码
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2024-05-28 10:24:02 +08:00 |
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Liphen
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d2f51d5967
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完成lab1大致实验框架
实现R型运算类指令的理想流水线设计
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2024-05-27 16:33:13 +08:00 |
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Liphen
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b3ba6c1c88
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完成lab2实验大致框架
实现I型和U型运算类指令的理想流水线设计
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2024-05-27 16:18:59 +08:00 |
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Liphen
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290f584dcc
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完成实验大致框架
实现乘除法指令的理想流水线设计实验
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2024-05-27 16:05:41 +08:00 |
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Liphen
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42b7355b45
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大致完成实验框架
实现访存指令的理想流水线设计实验
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2024-05-27 15:54:34 +08:00 |
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Liphen
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ecddfd545b
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完成实验大致框架
实现转移指令的理想流水线设计实验
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2024-05-27 15:50:41 +08:00 |
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Liphen
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0797cd651e
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修改顶层接口
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2024-05-27 15:40:25 +08:00 |
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Liphen
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d2bc851cf7
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完成气泡流水线大致代码框架
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2024-05-27 09:54:58 +08:00 |
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Liphen
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3b2ba2e43c
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删去多余代码
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2024-05-26 17:45:13 +08:00 |
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Liphen
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1e35953db9
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完成实验大致框架
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2024-05-26 16:35:52 +08:00 |
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Liphen
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2bc97b8b86
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修改sram信号定义
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2024-05-26 16:35:24 +08:00 |
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Liphen
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f50f173e74
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修复lsu的rdata逻辑
feat: 增加debugPro选项
开启时，增加增量调试输出，如sram的写回
删除debug sram信号
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2024-05-26 16:35:06 +08:00 |
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Liphen
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e191004c0f
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fix(lsu): mem级读数据处理错误
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2024-05-11 15:49:59 +08:00 |
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Liphen
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b9f0def62e
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exe访存时需要allow_to_go
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2024-05-11 14:56:38 +08:00 |
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Liphen
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140dad44a8
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Merge branch 'sram' of github.com:Ciliphen/DC-CA-SA-Lab into sram
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2024-05-11 14:50:03 +08:00 |
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Liphen
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ca1a6abe7b
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修复mem被阻塞时读数据错误问题
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2024-05-11 14:49:38 +08:00 |
Clo91eaf
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a765eed394
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fix(top_sram_wrapper) fix bit bug
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2024-05-11 14:15:32 +08:00 |
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Liphen
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5bd7124535
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feat(debug): 增加sram差分测试接口
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2024-05-11 11:40:26 +08:00 |
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Liphen
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4a9e3dc05f
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修改debug信号的wen为commit
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2024-05-09 19:16:02 +08:00 |
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Liphen
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be93752841
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修复jalr指令跳转目标问题
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2024-05-08 20:44:30 +08:00 |
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Liphen
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4f32948d0b
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修复访存级的冲刷问题
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2024-05-08 20:01:21 +08:00 |
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Liphen
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ed586e41b6
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fix: Fix FetchUnit PC initialization issue
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2024-05-08 16:56:28 +08:00 |
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Liphen
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9862402688
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fix: Fix FetchUnit PC initialization issue
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2024-05-08 13:04:57 +08:00 |
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Liphen
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59dc2337cb
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chore: Update Chisel dependencies to use version 6.1.0
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2024-05-07 10:33:44 +08:00 |
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Clo91eaf
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18f71c12d4
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unuse chisel test
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2024-05-07 01:47:10 +08:00 |
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Liphen
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333ced6e19
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fix(if): 修复第一个pc初始值问题
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2024-05-06 16:05:40 +08:00 |
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Liphen
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f6e8eeb381
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Merge branch 'sram' of github.com:Ciliphen/DC-CA-SA-Lab into sram
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2024-05-06 15:55:59 +08:00 |
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Liphen
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16043c72a0
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更新项目结构
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2024-05-06 15:54:28 +08:00 |
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Clo91eaf
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994f110808
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add chisel6 option
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2024-04-29 17:15:38 +08:00 |
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Liphen
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e03e7917db
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增加firtool
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2024-04-02 12:18:19 +08:00 |
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Liphen
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64336aaf1c
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refactor: 将ex信息在执行级后省略
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2024-03-22 23:29:02 +08:00 |
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Liphen
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be91a70924
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修改TestMain
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2024-03-22 23:18:11 +08:00 |
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Liphen
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e955c3d580
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更改CpuConfig
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2024-03-22 23:16:48 +08:00 |
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Liphen
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81b3915c46
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feat: 成功生成sram的verilog
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2024-03-22 22:57:04 +08:00 |
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Liphen
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0a20a7cda9
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feat: 升级chisel版本至5.0
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2024-03-22 22:56:41 +08:00 |
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Liphen
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6508b72858
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修改包名，修改各单元逻辑
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2024-03-22 22:45:48 +08:00 |
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Liphen
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703cd0b41c
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修改wb
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2024-03-22 21:14:19 +08:00 |
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Liphen
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8520961a64
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修改lsu
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2024-03-22 21:11:58 +08:00 |
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Liphen
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d16b70ea8d
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修改CpuConfig
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2024-03-22 15:07:18 +08:00 |
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Liphen
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f43763b32c
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修改bru，去除分支预测
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2024-03-22 15:00:13 +08:00 |
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Liphen
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e6decd7c82
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修改mdu
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2024-03-22 14:26:21 +08:00 |
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Liphen
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1ab2644cba
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修改if级逻辑
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2024-03-22 14:23:37 +08:00 |
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Liphen
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a69e4e907d
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删除不必要的文件
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2024-03-22 14:23:12 +08:00 |
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Liphen
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7e13a02cb4
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修改id级逻辑
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2024-03-22 14:18:56 +08:00 |
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Liphen
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2c7af2ce4b
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增加sram的顶层接口
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2024-03-22 11:13:19 +08:00 |
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Clo91eaf
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6274a62ba0
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remove .vscode from git.
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2024-03-15 00:42:14 +08:00 |
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Liphen
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b782293dac
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refactor: 修改异常变量名称
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2024-03-11 20:03:33 +08:00 |
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Liphen
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32005bb3e2
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删去部分无用定义
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2024-03-11 19:46:55 +08:00 |
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Liphen
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aaf97820d4
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fix(csr): 修复mem级valid无效时仍使用ex信息
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2024-03-11 19:27:23 +08:00 |