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大致完成实验框架 

实现访存指令的理想流水线设计实验
This commit is contained in:
Liphen 2024-05-27 15:54:34 +08:00
parent ecddfd545b
commit 42b7355b45
7 changed files with 6 additions and 121 deletions
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1
chisel/playground/src/Core.scala
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@ -41,7 +41,6 @@ class Core extends Module {
executeUnit.dataSram <> io.dataSram
// 执行单元
executeUnit.memoryStage <> memoryStage.executeUnit
executeUnit.fetchUnit <> fetchUnit.executeUnit
// 访存级缓存
memoryStage.memoryUnit <> memoryUnit.memoryStage
// 访存单元

26
chisel/playground/src/defines/isa/Instructions.scala
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@ -24,11 +24,10 @@ object SrcType {
}
object FuType {
def num = 4
def alu = "b00".U // arithmetic logic unit
def mdu = "b01".U // multiplication division unit
def lsu = "b10".U // load store unit
def bru = "b11".U // branch unit
def num = 3
def alu = 0.U // arithmetic logic unit
def mdu = 1.U // multiplication division unit
def lsu = 2.U // load store unit
def apply() = UInt(log2Up(num).W)
}
@ -59,23 +58,6 @@ object ALUOpType {
def isAdd(func: UInt) = func(5)
}
object BRUOpType {
def jal = "b1000".U
def jalr = "b1010".U
def beq = "b0000".U
def bne = "b0001".U
def blt = "b0100".U
def bge = "b0101".U
def bltu = "b0110".U
def bgeu = "b0111".U
def isBranch(func: UInt) = !func(3)
def isJump(func: UInt) = !isBranch(func)
def isAdd(func: UInt) = isJump(func)
def getBranchType(func: UInt) = func(2, 1)
def isBranchInvert(func: UInt) = func(0)
}
// load store unit
object LSUOpType {
def lb = "b0000".U

26
chisel/playground/src/defines/isa/RVI.scala
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@ -56,30 +56,6 @@ object RV32I_ALUInstr extends HasInstrType with CoreParameter {
)
}
object RV32I_BRUInstr extends HasInstrType {
def JAL = BitPat("b????????????????????_?????_1101111")
def JALR = BitPat("b????????????_?????_000_?????_1100111")
def BNE = BitPat("b???????_?????_?????_001_?????_1100011")
def BEQ = BitPat("b???????_?????_?????_000_?????_1100011")
def BLT = BitPat("b???????_?????_?????_100_?????_1100011")
def BGE = BitPat("b???????_?????_?????_101_?????_1100011")
def BLTU = BitPat("b???????_?????_?????_110_?????_1100011")
def BGEU = BitPat("b???????_?????_?????_111_?????_1100011")
val table = Array(
JAL -> List(InstrJ, FuType.bru, BRUOpType.jal),
JALR -> List(InstrI, FuType.bru, BRUOpType.jalr),
BEQ -> List(InstrB, FuType.bru, BRUOpType.beq),
BNE -> List(InstrB, FuType.bru, BRUOpType.bne),
BLT -> List(InstrB, FuType.bru, BRUOpType.blt),
BGE -> List(InstrB, FuType.bru, BRUOpType.bge),
BLTU -> List(InstrB, FuType.bru, BRUOpType.bltu),
BGEU -> List(InstrB, FuType.bru, BRUOpType.bgeu)
)
}
object RV32I_LSUInstr extends HasInstrType {
def LB = BitPat("b????????????_?????_000_?????_0000011")
def LH = BitPat("b????????????_?????_001_?????_0000011")
@ -134,6 +110,6 @@ object RV64IInstr extends HasInstrType {
}
object RVIInstr extends CoreParameter {
val table = RV32I_ALUInstr.table ++ RV32I_BRUInstr.table ++ RV32I_LSUInstr.table ++
val table = RV32I_ALUInstr.table ++ RV32I_LSUInstr.table ++
(if (XLEN == 64) RV64IInstr.table else Array.empty)
}

9
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
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@ -7,14 +7,8 @@ import cpu.defines._
import cpu.defines.Const._
import chisel3.util.experimental.BoringUtils
class BranchSignal extends Bundle {
val branch = Bool()
val target = UInt(XLEN.W)
}
class ExecuteUnit extends Module {
val io = IO(new Bundle {
val fetchUnit = Output(new BranchSignal())
val executeStage = Input(new DecodeUnitExecuteUnit())
val memoryStage = Output(new ExecuteUnitMemoryUnit())
val dataSram = new DataSram()
@ -31,9 +25,6 @@ class ExecuteUnit extends Module {
io.dataSram <> fu.dataSram
io.fetchUnit.branch := valid && fu.ctrl.flush
io.fetchUnit.target := fu.ctrl.target
io.memoryStage.data.pc := io.executeStage.data.pc
io.memoryStage.data.info := io.executeStage.data.info
io.memoryStage.data.src_info := io.executeStage.data.src_info

13
chisel/playground/src/pipeline/execute/Fu.scala
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@ -16,21 +16,12 @@ class Fu extends Module {
}
val dataSram = new DataSram()
val ctrl = new Bundle {
val flush = Output(Bool())
val target = Output(UInt(XLEN.W))
}
})
val alu = Module(new Alu()).io
val bru = Module(new Bru()).io
val mdu = Module(new Mdu()).io
val lsu = Module(new Lsu()).io
bru.in.pc := io.data.pc
bru.in.info := io.data.info
bru.in.src_info := io.data.src_info
alu.info := io.data.info
alu.src_info := io.data.src_info
@ -43,9 +34,5 @@ class Fu extends Module {
io.data.rd_info.wdata := DontCare
io.data.rd_info.wdata(FuType.alu) := alu.result
io.data.rd_info.wdata(FuType.bru) := io.data.pc + 4.U
io.data.rd_info.wdata(FuType.mdu) := mdu.result
io.ctrl.flush := bru.out.branch
io.ctrl.target := bru.out.target
}

44
chisel/playground/src/pipeline/execute/fu/Bru.scala
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@ -1,44 +0,0 @@
package cpu.pipeline
import chisel3._
import chisel3.util._
import cpu.defines._
import cpu.defines.Const._
class Bru extends Module {
val io = IO(new Bundle {
val in = new Bundle {
val pc = Input(UInt(XLEN.W))
val info = Input(new Info())
val src_info = Input(new SrcInfo())
}
val out = new Bundle {
val branch = Output(Bool())
val target = Output(UInt(XLEN.W))
}
})
val valid =
io.in.info.fusel === FuType.bru && io.in.info.valid
val src1 = io.in.src_info.src1_data
val src2 = io.in.src_info.src2_data
val op = io.in.info.op
val is_sub = !BRUOpType.isAdd(op)
val adder = (src1 +& (src2 ^ Fill(XLEN, is_sub))) + is_sub
val xor = src1 ^ src2
val sltu = !adder(XLEN)
val slt = xor(XLEN - 1) ^ sltu
val table = List(
BRUOpType.getBranchType(BRUOpType.beq) -> !xor.orR,
BRUOpType.getBranchType(BRUOpType.blt) -> slt,
BRUOpType.getBranchType(BRUOpType.bltu) -> sltu
)
val is_jump = BRUOpType.isJump(op)
val is_branch = (LookupTree(BRUOpType.getBranchType(op), table) ^ BRUOpType.isBranchInvert(op))
val is_jalr = op === BRUOpType.jalr
io.out.branch := valid & (is_jump | is_branch)
io.out.target := Mux(is_jalr, ((src1 + src2) & ~1.U(XLEN.W)), (io.in.pc + io.in.info.imm))
}

8
chisel/playground/src/pipeline/fetch/FetchUnit.scala
View File

@ -9,7 +9,6 @@ import cpu.defines._
class FetchUnit extends Module {
val io = IO(new Bundle {
val decodeStage = new FetchUnitDecodeUnit()
val executeUnit = Input(new BranchSignal())
val instSram = new InstSram()
})
@ -28,12 +27,7 @@ class FetchUnit extends Module {
val pc = RegEnable(io.instSram.addr, (PC_INIT - 4.U), state =/= boot)
io.instSram.addr := MuxCase(
pc + 4.U,
Seq(
io.executeUnit.branch -> io.executeUnit.target
)
)
io.instSram.addr := pc + 4.U
io.decodeStage.data.valid := state === receive
io.decodeStage.data.pc := pc