修改顶层接口

chisel/playground/src/defines/Bundles.scala

@@ -7,9 +7,9 @@ import cpu.defines.Const._
 import cpu.CpuConfig
 
 class ExtInterrupt extends Bundle {
-  val ei = Bool()
-  val ti = Bool()
-  val si = Bool()
+  val mei = Bool()
+  val mti = Bool()
+  val msi = Bool()
 }
 
 class SrcInfo extends Bundle {

difftest

@@ -1 +1 @@
-Subproject commit e2b04f50f1fa43f0153bac2a21f1bbcc98f050be
+Subproject commit 8fb9d90b00e02be2baa7536ffa43fe0a6d6dc7f6