Liphen
|
f7fb3c4677
|
fix(icache): 当地址未对齐时不应访存
|
2024-03-09 16:12:56 +08:00 |
Liphen
|
fdc8c2b11e
|
refactor(core): 修改clear信号,使逻辑更清晰
|
2024-02-25 17:09:12 +08:00 |
Liphen
|
9c3e70a3f4
|
重构instfifo
|
2024-01-23 14:38:47 +08:00 |
Liphen
|
8b4f9c71dd
|
refactor: 大致完成cpu的重构
|
2024-01-23 13:08:06 +08:00 |
Liphen
|
2e774df884
|
重构lsu
|
2024-01-22 16:43:02 +08:00 |
Liphen
|
413a7e22d2
|
重构exe unit
|
2024-01-22 15:40:38 +08:00 |
Liphen
|
b16eff1ba7
|
增加lsu的例外处理
|
2024-01-15 16:01:22 +08:00 |
Liphen
|
cd4345690b
|
增加sfence.vma
|
2024-01-15 14:59:55 +08:00 |
Liphen
|
2f3ff6e5dd
|
完成除vma指令外的框架
|
2024-01-15 13:36:44 +08:00 |
Liphen
|
6ca4ffcd86
|
refactor: 重构tlb
|
2024-01-13 13:13:31 +08:00 |
Liphen
|
08def4d1a0
|
refactor: decoder级重命名为decode
|
2024-01-07 16:57:36 +08:00 |
Liphen
|
eeb076b060
|
增加tlb相关常量定义
|
2024-01-03 16:17:36 +08:00 |
Liphen
|
78ca79384e
|
style: config统一为cpuConfig
|
2024-01-03 14:29:19 +08:00 |
Liphen
|
e81d0d2b8c
|
feat(lsu): 实现amo指令
|
2023-12-29 11:56:37 +08:00 |
Liphen
|
7470c6fb5f
|
增加fence,修复dcache的一处bug
|
2023-12-28 22:21:38 +08:00 |
Liphen
|
e6a6f250c9
|
fix(exe): 在exe提前访存
|
2023-12-25 21:19:31 +08:00 |
Liphen
|
108c529698
|
fix(cache): 将save状态改成wait,更符合作用
|
2023-12-25 15:45:30 +08:00 |
Liphen
|
a94958d7c9
|
refactor: 调整变量名,删除fuNum
|
2023-12-24 13:17:55 +08:00 |
Liphen
|
76c0f446da
|
feat: 增加dcache
|
2023-12-22 14:18:32 +08:00 |
Liphen
|
301199c756
|
feat: 添加icache成功生成Verilog
|
2023-12-21 15:24:57 +08:00 |
Liphen
|
6678952dde
|
Remove unused code and update variable assignment in Core and Ctrl classes
|
2023-12-11 15:20:40 +08:00 |
Liphen
|
cface2454d
|
Remove unused variables in Core and Csr classes
|
2023-12-11 15:08:56 +08:00 |
Liphen
|
7df36c2c38
|
refactor: 美化代码
|
2023-12-11 15:04:58 +08:00 |
Liphen
|
2a16d26278
|
feat: 通过所有测试用例
|
2023-12-07 21:14:40 +08:00 |
Liphen
|
f7ee8c4c87
|
成功生成verilog
|
2023-12-07 16:08:45 +08:00 |
Liphen
|
651f8319dd
|
feat: 增加MOU用于处理fence相关指令
|
2023-12-01 16:35:59 +08:00 |
Liphen
|
36840d6abe
|
refactor(exe): 重构部分跳转信号
|
2023-12-01 16:12:30 +08:00 |
Liphen
|
8a3e85b201
|
删除addr_err
|
2023-12-01 14:14:14 +08:00 |
Liphen
|
8c88660498
|
style: inst_info改为info
|
2023-11-30 18:51:47 +08:00 |
Liphen
|
1b3ce1e739
|
feat(mem): 增加acc例外
|
2023-11-29 17:20:45 +08:00 |
Liphen
|
aac7d1ccb8
|
fix(mem): 修复wstrb错误
|
2023-11-27 17:16:46 +08:00 |
Liphen
|
96899c5243
|
fix(bpu): 跳转addr计算错误
|
2023-11-27 15:49:07 +08:00 |
Liphen
|
b30026d57c
|
fix(dcache): 修改stall逻辑
|
2023-11-27 15:22:49 +08:00 |
Liphen
|
94352e1687
|
fix(ExeAccessMem): 修复mem en信号错误
|
2023-11-26 15:43:30 +08:00 |
Liphen
|
fbeb9413ab
|
fix(icache): 修复取指bug
|
2023-11-26 14:49:22 +08:00 |
Liphen
|
703b70adf4
|
修改变量名
|
2023-11-26 12:15:14 +08:00 |
Liphen
|
7daed5b3a5
|
修改信号名
|
2023-11-26 11:29:59 +08:00 |
Liphen
|
3000c5b424
|
fix: 可以正常取指令了
|
2023-11-24 12:05:47 +08:00 |
Liphen
|
31eadb3bf3
|
feat: 成功读取到指令
|
2023-11-23 21:51:57 +08:00 |
Liphen
|
6fbb02fffc
|
生成verilog
|
2023-11-23 16:08:39 +08:00 |
Liphen
|
a1f7cd92d0
|
去除大部分类型错误
|
2023-11-23 14:08:40 +08:00 |
Liphen
|
b75c49177e
|
增加需要实现的csr
|
2023-11-21 15:10:58 +08:00 |
Liphen
|
bb3942d119
|
修改bpu
|
2023-11-20 14:44:23 +08:00 |
Liphen
|
ec63ebc747
|
feat: 修改Decode模块
|
2023-11-17 15:59:02 +08:00 |
Liphen
|
ebbdd5b3b7
|
重构了下core
|
2023-11-14 12:11:53 +08:00 |
Liphen
|
f229789a12
|
feat: 修改并成功生成无cache的axi
|
2023-11-13 17:56:41 +08:00 |
Liphen
|
8913ae5da0
|
修改了部分前端设计,去除cache、tlb
|
2023-11-12 15:50:49 +08:00 |
Liphen
|
3c7beb03c6
|
增加pua-mips代码
|
2023-11-07 17:58:40 +08:00 |